cherryusb.git/port/fsdev/usb_glue_nation.c, branch master

update(port): change low level api from weak to extern, users must implement this

2026-09-26T14:02:25Z

Signed-off-by: sakumisu <1203593632@qq.com>

port/fsdev: log error when USBFS clock divider has no match

2026-08-29T07:37:44Z

Report an error through USB_LOG_ERR when SystemCoreClock does not match any supported 48/96/144/192/240 MHz divider case, instead of silently leaving the USBFS prescaler unconfigured.

fix(port/fsdev): address N32H4x glue review findings

2026-08-29T07:37:44Z

- usb_glue_nation.c: match usb_dc_low_level_init/deinit to the (void) weak stubs in usb_dc_fsdev.c and guard on g_usbdev_bus[0] (the old (uint8_t busid) signature read garbage at the no-arg call site) - usb_glue_nation.c: drop NVIC_PriorityGroupConfig from the driver hook; it reprograms SCB->AIRCR for the whole system, priority grouping now stays with board/application startup code - usb_glue_nation.c: derive the USBFS prescaler from SystemCoreClock at runtime instead of a per-part compile-time table (fixes N32H475 landing in the 240 MHz branch; adapts to any configured PLLCLK) - add docstrings to the functions touched by this diff

port/fsdev: add N32H4x (N32H47x_48x / N32H49x) USB FS device support

2026-08-29T07:37:44Z

Add full-speed USB device (USBFS) support for the Nations N32H4x family (N32H47x_48x and N32H49x), whose Synopsys USBFS core re-arranged the register and bit-field layout of the STM32 version: - usb_glue_nation.c: chip-level bring-up (48 MHz USB clock from PLL, DM/DP GPIO with a weak overridable hook, NVIC USB_FS_LP_IRQn dispatch) - usb_fsdev_reg.h: re-map USB_EPn/CNTR/ISTR/BTABLE/FN/DADDR register layout and every affected bit macro for N32H4x (32-bit EP registers, no BCDR; DP pull-up moved to CNTR.PU) - usb_dc_fsdev.c: N32H4x power-on sequence (clear PD, wait, clear FRST) and EP_ID position handling - README: document the supported N32H4x parts