cherryusb.git/port, branch v1.4.0

fix(port/dwc2): fix dwc2 rx fifo size, remove divided by 4

2024-09-08T14:11:38Z

fix(port/dwc2): reset dma burst then modify, clear HCINT intstatus first

2024-09-08T14:11:38Z

fix(port/dwc2): fix typo

2024-09-08T14:11:38Z

fix(port/ehci/usb_glue_ma35d0): fix typo

2024-09-02T10:54:53Z

update(port/dwc2/usb_hc_dwc2): power enable at last for common with other host ip

2024-09-01T03:59:11Z

Update usb_dc_dwc2.c

2024-08-29T01:43:11Z

According to DS, the status register is W1C, |= will read the register first, write 1 to the corresponding bit, then write the register, if there is more than one status, it will be cleared by mistake. I'm not sure if other IP dcd's have the same problem?

fix(port/bl): overflow check

2024-08-25T12:19:33Z

feat(port/chipidea): add chipidea port, add nxp mxc glue for chipidea and ehci

2024-08-25T12:19:25Z

update(port/hpm): check resume in port change

2024-08-23T14:36:14Z

port: hpmicro: add USBH_USE_CUSTOM_ISR add USBD_USE_CUSTOM_ISR to control isr

2024-08-23T05:57:45Z

- add USBH_USE_CUSTOM_ISR add USBD_USE_CUSTOM_ISR to control isr Signed-off-by: Zhihong Chen