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video split tranfer, every transfer with one ep_mps
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With the change from cherry-embedded#260, this buffer no longer needs to be so large. It can be reduced to the save a lot of memory.
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error and set lun=0, refs:#259
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video demo and export CONFIG_USB_DWC2_DMA_ENABLE
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every transfer will reset this bits, so we need restore it. remove ununsed iso imcomplete isr
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CONFIG_USBDEV_MSC_MAX_BUFSIZE
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Descriptor, we do not request other speed desc as default
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host ip
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According to DS, the status register is W1C, |= will read the register first, write 1 to the corresponding bit, then write the register, if there is more than one status, it will be cleared by mistake. I'm not sure if other IP dcd's have the same problem?
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