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host ip
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According to DS, the status register is W1C, |= will read the register first, write 1 to the corresponding bit, then write the register, if there is more than one status, it will be cleared by mistake. I'm not sure if other IP dcd's have the same problem?
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- add USBH_USE_CUSTOM_ISR add USBD_USE_CUSTOM_ISR to control isr
Signed-off-by: Zhihong Chen <[email protected]>
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Signed-off-by: Zhihong Chen <[email protected]>
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Signed-off-by: Zhihong Chen <[email protected]>
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version 4.3
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- update init and deinit
Signed-off-by: Zhihong Chen <[email protected]>
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usb_hc_e(o)hci_priv to usb_hc_e(o)hci
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- update usb_glue_hpm
Signed-off-by: Zhihong Chen <[email protected]>
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