From 73712a1b545a6cd1352ea2a35dcb00e5e8063b39 Mon Sep 17 00:00:00 2001 From: sakumisu <1203593632@qq.com> Date: Wed, 22 Jun 2022 22:31:58 +0800 Subject: add stm32h743 host demo --- demo/stm32/usb_host/stm32h743xih6/.mxproject | 25 + .../stm32h743xih6/Core/Inc/FreeRTOSConfig.h | 312 ++++++++ demo/stm32/usb_host/stm32h743xih6/Core/Inc/main.h | 71 ++ .../stm32h743xih6/Core/Inc/stm32h7xx_hal_conf.h | 511 ++++++++++++ .../usb_host/stm32h743xih6/Core/Inc/stm32h7xx_it.h | 70 ++ .../usb_host/stm32h743xih6/Core/Inc/usb_config.h | 132 ++++ demo/stm32/usb_host/stm32h743xih6/Core/Src/main.c | 366 +++++++++ .../stm32h743xih6/Core/Src/stm32h7xx_hal_msp.c | 248 ++++++ .../usb_host/stm32h743xih6/Core/Src/stm32h7xx_it.c | 226 ++++++ .../stm32h743xih6/Core/Src/system_stm32h7xx.c | 421 ++++++++++ .../stm32h743xih6/MDK-ARM/startup_stm32h743xx.s | 611 ++++++++++++++ .../stm32h743xih6/MDK-ARM/stm32h743xih6.uvoptx | 878 +++++++++++++++++++++ .../stm32h743xih6/MDK-ARM/stm32h743xih6.uvprojx | 649 +++++++++++++++ .../stm32/usb_host/stm32h743xih6/stm32h743xih6.ioc | 187 +++++ 14 files changed, 4707 insertions(+) create mode 100644 demo/stm32/usb_host/stm32h743xih6/.mxproject create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Inc/FreeRTOSConfig.h create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Inc/main.h create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_hal_conf.h create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_it.h create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Inc/usb_config.h create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Src/main.c create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_hal_msp.c create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_it.c create mode 100644 demo/stm32/usb_host/stm32h743xih6/Core/Src/system_stm32h7xx.c create mode 100644 demo/stm32/usb_host/stm32h743xih6/MDK-ARM/startup_stm32h743xx.s create mode 100644 demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvoptx create mode 100644 demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvprojx create mode 100644 demo/stm32/usb_host/stm32h743xih6/stm32h743xih6.ioc diff --git a/demo/stm32/usb_host/stm32h743xih6/.mxproject b/demo/stm32/usb_host/stm32h743xih6/.mxproject new file mode 100644 index 00000000..97c0c877 --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/.mxproject @@ -0,0 +1,25 @@ +[PreviousLibFiles] +LibFiles=Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedKeilFiles] +SourceFiles=..\Core\Src\main.c;..\Core\Src\stm32h7xx_it.c;..\Core\Src\stm32h7xx_hal_msp.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c;..\Core\Src/system_stm32h7xx.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c;..\Core\Src/system_stm32h7xx.c;..\Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;; +HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc; +CDefines=USE_HAL_DRIVER;STM32H743xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=C:/Users/lvjiazhen/Desktop/CherryUSB/demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_it.h +HeaderFiles#1=C:/Users/lvjiazhen/Desktop/CherryUSB/demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_hal_conf.h +HeaderFiles#2=C:/Users/lvjiazhen/Desktop/CherryUSB/demo/stm32/usb_host/stm32h743xih6/Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=C:/Users/lvjiazhen/Desktop/CherryUSB/demo/stm32/usb_host/stm32h743xih6/Core/Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=C:/Users/lvjiazhen/Desktop/CherryUSB/demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_it.c +SourceFiles#1=C:/Users/lvjiazhen/Desktop/CherryUSB/demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_hal_msp.c +SourceFiles#2=C:/Users/lvjiazhen/Desktop/CherryUSB/demo/stm32/usb_host/stm32h743xih6/Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=C:/Users/lvjiazhen/Desktop/CherryUSB/demo/stm32/usb_host/stm32h743xih6/Core/Src +SourceFiles=; + diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Inc/FreeRTOSConfig.h b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/FreeRTOSConfig.h new file mode 100644 index 00000000..fb4644fe --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/FreeRTOSConfig.h @@ -0,0 +1,312 @@ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "stm32h7xx_hal.h" + +//针对不同的编译器调用不同的stdint.h文件 +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + #include + extern uint32_t SystemCoreClock; +#endif + +//断言 + +#define configASSERT(x) +/************************************************************************ + * FreeRTOS基础配置配置选项 + *********************************************************************/ +/* 置1：RTOS使用抢占式调度器；置0：RTOS使用协作式调度器（时间片） + * + * 注：在多任务管理机制上，操作系统可以分为抢占式和协作式两种。 + * 协作式操作系统是任务主动释放CPU后，切换到下一个任务。 + * 任务切换的时机完全取决于正在运行的任务。 + */ +#define configUSE_PREEMPTION 1 + +//1使能时间片调度(默认式使能的) +#define configUSE_TIME_SLICING 1 + +/* 某些运行FreeRTOS的硬件有两种方法选择下一个要执行的任务： + * 通用方法和特定于硬件的方法（以下简称“特殊方法”）。 + * + * 通用方法： + * 1.configUSE_PORT_OPTIMISED_TASK_SELECTION 为 0 或者硬件不支持这种特殊方法。 + * 2.可以用于所有FreeRTOS支持的硬件 + * 3.完全用C实现，效率略低于特殊方法。 + * 4.不强制要求限制最大可用优先级数目 + * 特殊方法： + * 1.必须将configUSE_PORT_OPTIMISED_TASK_SELECTION设置为1。 + * 2.依赖一个或多个特定架构的汇编指令（一般是类似计算前导零[CLZ]指令）。 + * 3.比通用方法更高效 + * 4.一般强制限定最大可用优先级数目为32 + * 一般是硬件计算前导零指令，如果所使用的，MCU没有这些硬件指令的话此宏应该设置为0！ + */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + +/* 置1：使能低功耗tickless模式；置0：保持系统节拍（tick）中断一直运行 + * 假设开启低功耗的话可能会导致下载出现问题，因为程序在睡眠中,可用以下办法解决 + * + * 下载方法： + * 1.将开发版正常连接好 + * 2.按住复位按键，点击下载瞬间松开复位按键 + * + * 1.通过跳线帽将 BOOT 0 接高电平(3.3V) + * 2.重新上电，下载 + * + * 1.使用FlyMcu擦除一下芯片，然后进行下载 + * STMISP -> 清除芯片(z) + */ +#define configUSE_TICKLESS_IDLE 0 + +/* + * 写入实际的CPU内核时钟频率，也就是CPU指令执行频率，通常称为Fclk + * Fclk为供给CPU内核的时钟信号，我们所说的cpu主频为 XX MHz， + * 就是指的这个时钟信号，相应的，1/Fclk即为cpu时钟周期； + */ +#define configCPU_CLOCK_HZ (SystemCoreClock) + +//RTOS系统节拍中断的频率。即一秒中断的次数，每次中断RTOS都会进行任务调度 +#define configTICK_RATE_HZ (( TickType_t )1000) + +//可使用的最大优先级 +#define configMAX_PRIORITIES (32) + +//空闲任务使用的堆栈大小 +#define configMINIMAL_STACK_SIZE ((unsigned short)128) + +//任务名字字符串长度 +#define configMAX_TASK_NAME_LEN (16) + + //系统节拍计数器变量数据类型，1表示为16位无符号整形，0表示为32位无符号整形 +#define configUSE_16_BIT_TICKS 0 + +//空闲任务放弃CPU使用权给其他同优先级的用户任务 +#define configIDLE_SHOULD_YIELD 1 + +//启用队列 +#define configUSE_QUEUE_SETS 1 + +//开启任务通知功能，默认开启 +#define configUSE_TASK_NOTIFICATIONS 1 + +//使用互斥信号量 +#define configUSE_MUTEXES 1 + +//使用递归互斥信号量 +#define configUSE_RECURSIVE_MUTEXES 0 + +//为1时使用计数信号量 +#define configUSE_COUNTING_SEMAPHORES 1 + +/* 设置可以注册的信号量和消息队列个数 */ +#define configQUEUE_REGISTRY_SIZE 10 + +#define configUSE_APPLICATION_TASK_TAG 0 + + +/***************************************************************** + FreeRTOS与内存申请有关配置选项 +*****************************************************************/ +//支持动态内存申请 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +//支持静态内存 +#define configSUPPORT_STATIC_ALLOCATION 0 +//系统所有总的堆大小 +#define configTOTAL_HEAP_SIZE ((size_t)(36*1024)) + + +/*************************************************************** + FreeRTOS与钩子函数有关的配置选项 +**************************************************************/ +/* 置1：使用空闲钩子（Idle Hook类似于回调函数）；置0：忽略空闲钩子 + * + * 空闲任务钩子是一个函数，这个函数由用户来实现， + * FreeRTOS规定了函数的名字和参数：void vApplicationIdleHook(void )， + * 这个函数在每个空闲任务周期都会被调用 + * 对于已经删除的RTOS任务，空闲任务可以释放分配给它们的堆栈内存。 + * 因此必须保证空闲任务可以被CPU执行 + * 使用空闲钩子函数设置CPU进入省电模式是很常见的 + * 不可以调用会引起空闲任务阻塞的API函数 + */ +#define configUSE_IDLE_HOOK 0 + +/* 置1：使用时间片钩子（Tick Hook）；置0：忽略时间片钩子 + * + * + * 时间片钩子是一个函数，这个函数由用户来实现， + * FreeRTOS规定了函数的名字和参数：void vApplicationTickHook(void ) + * 时间片中断可以周期性的调用 + * 函数必须非常短小，不能大量使用堆栈， + * 不能调用以”FromISR" 或 "FROM_ISR”结尾的API函数 + */ + /*xTaskIncrementTick函数是在xPortSysTickHandler中断函数中被调用的。因此，vApplicationTickHook()函数执行的时间必须很短才行*/ +#define configUSE_TICK_HOOK 0 + +//使用内存申请失败钩子函数 +#define configUSE_MALLOC_FAILED_HOOK 0 + +/* + * 大于0时启用堆栈溢出检测功能，如果使用此功能 + * 用户必须提供一个栈溢出钩子函数，如果使用的话 + * 此值可以为1或者2，因为有两种栈溢出检测方法 */ +#define configCHECK_FOR_STACK_OVERFLOW 0 + + +/******************************************************************** + FreeRTOS与运行时间和任务状态收集有关的配置选项 +**********************************************************************/ +//启用运行时间统计功能 +#define configGENERATE_RUN_TIME_STATS 0 + //启用可视化跟踪调试 +#define configUSE_TRACE_FACILITY 0 +/* 与宏configUSE_TRACE_FACILITY同时为1时会编译下面3个函数 + * prvWriteNameToBuffer() + * vTaskList(), + * vTaskGetRunTimeStats() +*/ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + + +/******************************************************************** + FreeRTOS与协程有关的配置选项 +*********************************************************************/ +//启用协程，启用协程以后必须添加文件croutine.c +#define configUSE_CO_ROUTINES 0 +//协程的有效优先级数目 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + + +/*********************************************************************** + FreeRTOS与软件定时器有关的配置选项 +**********************************************************************/ + //启用软件定时器 +#define configUSE_TIMERS 1 +//软件定时器优先级 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-1) +//软件定时器队列长度 +#define configTIMER_QUEUE_LENGTH 10 +//软件定时器任务堆栈大小 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE*2) + +/************************************************************ + FreeRTOS可选函数配置选项 +************************************************************/ +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +//#define INCLUDE_xTaskGetCurrentTaskHandle 1 +//#define INCLUDE_uxTaskGetStackHighWaterMark 0 +//#define INCLUDE_xTaskGetIdleTaskHandle 0 + + +/****************************************************************** + FreeRTOS与中断有关的配置选项 +******************************************************************/ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 +#endif +//中断最低优先级 +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +//系统可管理的最高中断优先级 +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) /* 240 */ + +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - 4) ) + + +/**************************************************************** + FreeRTOS与中断服务函数有关的配置选项 +****************************************************************/ +#define xPortPendSVHandler PendSV_Handler +#define vPortSVCHandler SVC_Handler + + +/* 以下为使用Percepio Tracealyzer需要的东西，不需要时将 configUSE_TRACE_FACILITY 定义为 0 */ +#if ( configUSE_TRACE_FACILITY == 1 ) +#include "trcRecorder.h" +#define INCLUDE_xTaskGetCurrentTaskHandle 1 // 启用一个可选函数（该函数被 Trace源码使用，默认该值为0 表示不用） +#endif + + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Inc/main.h b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/main.h new file mode 100644 index 00000000..bef7be5d --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_hal_conf.h b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_hal_conf.h new file mode 100644 index 00000000..8cf4c0e0 --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_hal_conf.h @@ -0,0 +1,511 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_CONF_H +#define STM32H7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_FMAC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_OTFDEC_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HRTIM_MODULE_ENABLED */ +/* #define HAL_HSEM_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SWPMI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +#define HAL_HCD_MODULE_ENABLED +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal oscillator (CSI) default value. + * This value is the default CSI value after Reset. + */ +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ +#define USE_SPI_CRC 0U /*!< use CRC in SPI */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################### Ethernet Configuration ######################### */ +#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */ +#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */ + +#define ETH_MAC_ADDR0 (0x02UL) +#define ETH_MAC_ADDR1 (0x00UL) +#define ETH_MAC_ADDR2 (0x00UL) +#define ETH_MAC_ADDR3 (0x00UL) +#define ETH_MAC_ADDR4 (0x00UL) +#define ETH_MAC_ADDR5 (0x00UL) + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_MDMA_MODULE_ENABLED + #include "stm32h7xx_hal_mdma.h" +#endif /* HAL_MDMA_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32h7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32h7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32h7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32h7xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32h7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED + #include "stm32h7xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED + #include "stm32h7xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED + #include "stm32h7xx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32h7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32h7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32h7xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32h7xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32h7xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32h7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7xx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32h7xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_it.h b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_it.h new file mode 100644 index 00000000..195e1a13 --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/stm32h7xx_it.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_IT_H +#define __STM32H7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void OTG_HS_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Inc/usb_config.h b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/usb_config.h new file mode 100644 index 00000000..39c77df6 --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Inc/usb_config.h @@ -0,0 +1,132 @@ +#ifndef _USB_CONFIG_H +#define _USB_CONFIG_H + +/* USB common Configuration */ +#ifndef CONFIG_USB_DBG_LEVEL +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +#ifndef CONFIG_USB_PRINTF +#define CONFIG_USB_PRINTF printf +#endif + +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* USB DEVICE Configuration */ +/* core */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 256 +#endif + +#ifndef CONFIG_USBDEV_DESC_CHECK +#define CONFIG_USBDEV_DESC_CHECK 0 +#endif + +#ifndef CONFIG_USBDEV_TEST_MODE +#define CONFIG_USBDEV_TEST_MODE 0 +#endif + +/* cdc class */ +// #define CONFIG_USBDEV_CDC_ACM_UART + +/* msc class */ +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifdef CONFIG_USBDEV_MSC_THREAD +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif +#endif + +/* audio class */ +#ifndef CONFIG_USBDEV_AUDIO_VERSION +#define CONFIG_USBDEV_AUDIO_VERSION 0x0100 +#endif + +#ifndef CONFIG_USBDEV_AUDIO_MAX_CHANNEL +#define CONFIG_USBDEV_AUDIO_MAX_CHANNEL 2 +#endif + +/* USB HOST Configuration */ +#ifndef CONFIG_USBHOST_RHPORTS +#define CONFIG_USBHOST_RHPORTS 1 +#endif + +#ifndef CONFIG_USBHOST_EHPORTS +#define CONFIG_USBHOST_EHPORTS 4 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +#ifndef CONFIG_USBHOST_INTF_NUM +#define CONFIG_USBHOST_INTF_NUM 6 +#endif + +#ifndef CONFIG_USBHOST_EP_NUM +#define CONFIG_USBHOST_EP_NUM 4 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 5000 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +#ifndef CONFIG_USBHOST_HPWORKQ_PRIO +#define CONFIG_USBHOST_HPWORKQ_PRIO 5 +#endif +#ifndef CONFIG_USBHOST_HPWORKQ_STACKSIZE +#define CONFIG_USBHOST_HPWORKQ_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBHOST_LPWORKQ_PRIO +#define CONFIG_USBHOST_LPWORKQ_PRIO 1 +#endif +#ifndef CONFIG_USBHOST_LPWORKQ_STACKSIZE +#define CONFIG_USBHOST_LPWORKQ_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 4 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBHOST_DEV_NAMELEN +#define CONFIG_USBHOST_DEV_NAMELEN 16 +#endif + +#define CONFIG_USBHOST_ASYNCH +//#define CONFIG_USBHOST_GET_STRING_DESC + +/* EHCI Configuration */ +#define CONFIG_USB_EHCI_HCCR_BASE (0x20072000) +#define CONFIG_USB_EHCI_HCOR_BASE (0x20072000 + 0x10) +#define CONFIG_USB_EHCI_QH_NUM (10) +#define CONFIG_USB_EHCI_QTD_NUM (10) +// #define CONFIG_USB_EHCI_INFO_ENABLE +#define CONFIG_USB_ECHI_HCOR_RESERVED_DISABLE +// #define CONFIG_USB_EHCI_CONFIGFLAG + +#endif diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Src/main.c b/demo/stm32/usb_host/stm32h743xih6/Core/Src/main.c new file mode 100644 index 00000000..89736b13 --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Src/main.c @@ -0,0 +1,366 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "FreeRTOS.h" +#include "task.h" +#include "stdio.h" +#include "usbh_core.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +UART_HandleTypeDef huart1; + +HCD_HandleTypeDef hhcd_USB_OTG_HS; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_USB_OTG_HS_HCD_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +int fputc(int ch, FILE *f) +{ + HAL_UART_Transmit(&huart1,(uint8_t*)&ch,1,1000); + return ch; +} + +void usb_hc_low_level_init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */ + + /* USER CODE END USB_OTG_HS_MspInit 0 */ + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL3.PLL3M = 25; + PeriphClkInitStruct.PLL3.PLL3N = 240; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 5; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Enable USB Voltage detector + */ + HAL_PWREx_EnableUSBVoltageDetector(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USB_OTG_HS GPIO Configuration + PB15 ------> USB_OTG_HS_DP + PB14 ------> USB_OTG_HS_DM + */ + GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_OTG2_FS; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + /* USB_OTG_HS interrupt Init */ + HAL_NVIC_SetPriority(OTG_HS_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(OTG_HS_IRQn); + /* USER CODE BEGIN USB_OTG_HS_MspInit 1 */ + + /* USER CODE END USB_OTG_HS_MspInit 1 */ +} +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* Enable I-Cache---------------------------------------------------------*/ + SCB_EnableICache(); + + /* Enable D-Cache---------------------------------------------------------*/ +// SCB_EnableDCache(); + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + //MX_USB_OTG_HS_HCD_Init(); + /* USER CODE BEGIN 2 */ + usbh_initialize(); + printf("Start usb host task...\r\n"); + vTaskStartScheduler(); + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + /** Macro to configure the PLL clock source + */ + __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + RCC_OscInitStruct.PLL.PLLN = 160; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USB_OTG_HS Initialization Function + * @param None + * @retval None + */ +static void MX_USB_OTG_HS_HCD_Init(void) +{ + + /* USER CODE BEGIN USB_OTG_HS_Init 0 */ + + /* USER CODE END USB_OTG_HS_Init 0 */ + + /* USER CODE BEGIN USB_OTG_HS_Init 1 */ + + /* USER CODE END USB_OTG_HS_Init 1 */ + hhcd_USB_OTG_HS.Instance = USB_OTG_HS; + hhcd_USB_OTG_HS.Init.Host_channels = 16; + hhcd_USB_OTG_HS.Init.speed = HCD_SPEED_FULL; + hhcd_USB_OTG_HS.Init.dma_enable = ENABLE; + hhcd_USB_OTG_HS.Init.phy_itface = USB_OTG_EMBEDDED_PHY; + hhcd_USB_OTG_HS.Init.Sof_enable = DISABLE; + hhcd_USB_OTG_HS.Init.low_power_enable = DISABLE; + hhcd_USB_OTG_HS.Init.use_external_vbus = DISABLE; + if (HAL_HCD_Init(&hhcd_USB_OTG_HS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_OTG_HS_Init 2 */ + + /* USER CODE END USB_OTG_HS_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_hal_msp.c b/demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_hal_msp.c new file mode 100644 index 00000000..f9f5afe8 --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_hal_msp.c @@ -0,0 +1,248 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA10 ------> USART1_RX + PA9 ------> USART1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA10 ------> USART1_RX + PA9 ------> USART1_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10|GPIO_PIN_9); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + +} + +/** +* @brief HCD MSP Initialization +* This function configures the hardware resources used in this example +* @param hhcd: HCD handle pointer +* @retval None +*/ +void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(hhcd->Instance==USB_OTG_HS) + { + /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */ + + /* USER CODE END USB_OTG_HS_MspInit 0 */ + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL3.PLL3M = 25; + PeriphClkInitStruct.PLL3.PLL3N = 240; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 5; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Enable USB Voltage detector + */ + HAL_PWREx_EnableUSBVoltageDetector(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USB_OTG_HS GPIO Configuration + PB15 ------> USB_OTG_HS_DP + PB14 ------> USB_OTG_HS_DM + */ + GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_OTG2_FS; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + /* USB_OTG_HS interrupt Init */ + HAL_NVIC_SetPriority(OTG_HS_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(OTG_HS_IRQn); + /* USER CODE BEGIN USB_OTG_HS_MspInit 1 */ + + /* USER CODE END USB_OTG_HS_MspInit 1 */ + } + +} + +/** +* @brief HCD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hhcd: HCD handle pointer +* @retval None +*/ +void HAL_HCD_MspDeInit(HCD_HandleTypeDef* hhcd) +{ + if(hhcd->Instance==USB_OTG_HS) + { + /* USER CODE BEGIN USB_OTG_HS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_HS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_HS_CLK_DISABLE(); + + /**USB_OTG_HS GPIO Configuration + PB15 ------> USB_OTG_HS_DP + PB14 ------> USB_OTG_HS_DM + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_15|GPIO_PIN_14); + + /* USB_OTG_HS interrupt DeInit */ + HAL_NVIC_DisableIRQ(OTG_HS_IRQn); + /* USER CODE BEGIN USB_OTG_HS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_HS_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_it.c b/demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_it.c new file mode 100644 index 00000000..c7b43efc --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Src/stm32h7xx_it.c @@ -0,0 +1,226 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern HCD_HandleTypeDef hhcd_USB_OTG_HS; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +//void SVC_Handler(void) +//{ +// /* USER CODE BEGIN SVCall_IRQn 0 */ + +// /* USER CODE END SVCall_IRQn 0 */ +// /* USER CODE BEGIN SVCall_IRQn 1 */ + +// /* USER CODE END SVCall_IRQn 1 */ +//} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +//void PendSV_Handler(void) +//{ +// /* USER CODE BEGIN PendSV_IRQn 0 */ + +// /* USER CODE END PendSV_IRQn 0 */ +// /* USER CODE BEGIN PendSV_IRQn 1 */ + +// /* USER CODE END PendSV_IRQn 1 */ +//} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ +extern void xPortSysTickHandler(void); + #if (INCLUDE_xTaskGetSchedulerState == 1 ) + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + { + #endif /* INCLUDE_xTaskGetSchedulerState */ + xPortSysTickHandler(); + #if (INCLUDE_xTaskGetSchedulerState == 1 ) + } + #endif /* INCLUDE_xTaskGetSchedulerState */ + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} +/******************************************************************************/ +/* STM32H7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USB On The Go HS global interrupt. + */ +//void OTG_HS_IRQHandler(void) +//{ +// /* USER CODE BEGIN OTG_HS_IRQn 0 */ + +// /* USER CODE END OTG_HS_IRQn 0 */ +// HAL_HCD_IRQHandler(&hhcd_USB_OTG_HS); +// /* USER CODE BEGIN OTG_HS_IRQn 1 */ + +// /* USER CODE END OTG_HS_IRQn 1 */ +//} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/stm32/usb_host/stm32h743xih6/Core/Src/system_stm32h7xx.c b/demo/stm32/usb_host/stm32h743xih6/Core/Src/system_stm32h7xx.c new file mode 100644 index 00000000..96f8a5bf --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/Core/Src/system_stm32h7xx.c @@ -0,0 +1,421 @@ +/** + ****************************************************************************** + * @file system_stm32h7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32h7xx.h" +#include +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ +/* #define DATA_IN_D2_SRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting and vector table location + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#if defined (DATA_IN_D2_SRAM) + __IO uint32_t tmpreg; +#endif /* DATA_IN_D2_SRAM */ + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + +#if defined(D3_SRAM_BASE) + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; +#else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x02020200; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x01FF0000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + +#if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } +#endif + +#if defined (DATA_IN_D2_SRAM) + /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ + + tmpreg = RCC->AHB2ENR; + (void) tmpreg; +#endif /* DATA_IN_D2_SRAM */ + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif /* VECT_TAB_SRAM */ + +#else + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ +#else + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#endif /*DUAL_CORE && CORE_CM4*/ + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = CSI_VALUE; + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ +#if defined (RCC_D1CFGR_D1CPRE) + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/startup_stm32h743xx.s b/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/startup_stm32h743xx.s new file mode 100644 index 00000000..752fec4b --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/startup_stm32h743xx.s @@ -0,0 +1,611 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32h743xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x1000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x1000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT HRTIM1_Master_IRQHandler [WEAK] + EXPORT HRTIM1_TIMA_IRQHandler [WEAK] + EXPORT HRTIM1_TIMB_IRQHandler [WEAK] + EXPORT HRTIM1_TIMC_IRQHandler [WEAK] + EXPORT HRTIM1_TIMD_IRQHandler [WEAK] + EXPORT HRTIM1_TIME_IRQHandler [WEAK] + EXPORT HRTIM1_FLT_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SAI3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +OTG_FS_EP1_OUT_IRQHandler +OTG_FS_EP1_IN_IRQHandler +OTG_FS_WKUP_IRQHandler +OTG_FS_IRQHandler +DMAMUX1_OVR_IRQHandler +HRTIM1_Master_IRQHandler +HRTIM1_TIMA_IRQHandler +HRTIM1_TIMB_IRQHandler +HRTIM1_TIMC_IRQHandler +HRTIM1_TIMD_IRQHandler +HRTIM1_TIME_IRQHandler +HRTIM1_FLT_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SAI3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +WAKEUP_PIN_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvoptx b/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvoptx new file mode 100644 index 00000000..2a14c094 --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvoptx @@ -0,0 +1,878 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + stm32h743xih6 + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Fire CMSIS-DAP" -UFS-00001418 -O239 -S10 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743XIHx$CMSIS\Flash\STM32H7x_2048.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743XIHx$CMSIS\Flash\STM32H7x_2048.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743XIHx$CMSIS\Flash\STM32H7x_2048.FLM) + + + + + 0 + 0 + 1415 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + + + + + 1 + 0 + 1415 + 1 +
134227914
+ 0 + 0 + 0 + 0 + 0 + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + + \\stm32h743xih6\../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c\1415 + + + 2 + 0 + 1432 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + + + + + 3 + 0 + 1432 + 1 +
134227964
+ 0 + 0 + 0 + 0 + 0 + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + + \\stm32h743xih6\../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c\1432 + + + 4 + 0 + 1447 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + + + + + 5 + 0 + 1496 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 2000000 + + + + + + Application/MDK-ARM + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + startup_stm32h743xx.s + startup_stm32h743xx.s + 0 + 0 + + + + + Application/User/Core + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ../Core/Src/main.c + main.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ../Core/Src/stm32h7xx_it.c + stm32h7xx_it.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ../Core/Src/stm32h7xx_hal_msp.c + stm32h7xx_hal_msp.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\usb_host.c + usb_host.c + 0 + 0 + + + + + Drivers/STM32H7xx_HAL_Driver + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c + stm32h7xx_hal_cortex.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c + stm32h7xx_hal_rcc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c + stm32h7xx_hal_rcc_ex.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c + stm32h7xx_hal_flash.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c + stm32h7xx_hal_flash_ex.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c + stm32h7xx_hal_gpio.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c + stm32h7xx_hal_hsem.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c + stm32h7xx_hal_dma.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c + stm32h7xx_hal_dma_ex.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c + stm32h7xx_hal_mdma.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c + stm32h7xx_hal_pwr.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c + stm32h7xx_hal_pwr_ex.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c + stm32h7xx_hal.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c + stm32h7xx_hal_i2c.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c + stm32h7xx_hal_i2c_ex.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c + stm32h7xx_hal_exti.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c + stm32h7xx_hal_tim.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c + stm32h7xx_hal_tim_ex.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c + stm32h7xx_hal_uart.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c + stm32h7xx_hal_uart_ex.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + stm32h7xx_hal_hcd.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c + stm32h7xx_ll_usb.c + 0 + 0 + + + + + Drivers/CMSIS + 0 + 0 + 0 + 0 + + 4 + 28 + 1 + 0 + 0 + 0 + ../Core/Src/system_stm32h7xx.c + system_stm32h7xx.c + 0 + 0 + + + + + FreeRTOS + 0 + 0 + 0 + 0 + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\..\third_party\FreeRTOS-10.4\croutine.c + croutine.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\..\third_party\FreeRTOS-10.4\event_groups.c + event_groups.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\..\third_party\FreeRTOS-10.4\list.c + list.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\..\..\third_party\FreeRTOS-10.4\queue.c + queue.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\..\third_party\FreeRTOS-10.4\tasks.c + tasks.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\..\third_party\FreeRTOS-10.4\timers.c + timers.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ..\..\..\..\..\third_party\FreeRTOS-10.4\portable\MemMang\heap_4.c + heap_4.c + 0 + 0 + + + 5 + 36 + 1 + 0 + 0 + 0 + ..\..\..\..\..\third_party\FreeRTOS-10.4\portable\GCC\ARM_CM7\r0p1\port.c + port.c + 0 + 0 + + + + + CherryUSB + 1 + 0 + 0 + 0 + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\..\..\core\usbh_core.c + usbh_core.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\..\..\osal\usb_osal_freertos.c + usb_osal_freertos.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\..\..\osal\usb_workq.c + usb_workq.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\..\..\class\cdc\usbh_cdc_acm.c + usbh_cdc_acm.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\..\..\class\hid\usbh_hid.c + usbh_hid.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\..\..\class\msc\usbh_msc.c + usbh_msc.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\..\..\port\dwc2\usb_hc_dwc2.c + usb_hc_dwc2.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvprojx b/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvprojx new file mode 100644 index 00000000..da51abe3 --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvprojx @@ -0,0 +1,649 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + stm32h743xih6 + 0x4 + ARM-ADS + 6140001::V6.14.1::ARMCLANG + 6140001::V6.14.1::ARMCLANG + 1 + + + STM32H743XIHx + STMicroelectronics + Keil.STM32H7xx_DFP.2.5.0 + https://www.keil.com/pack/ + IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE TZ + + + + 0 + + + + + + + + + + + $$Device:STM32H743XIHx$CMSIS\SVD\STM32H743.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + stm32h743xih6\ + stm32h743xih6 + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x24000000 + 0x80000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER,STM32H743xx,STM32H7,CONFIG_USBHOST_HIGH_WORKQ + + ../Core/Inc;../Drivers/STM32H7xx_HAL_Driver/Inc;../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32H7xx/Include;../Drivers/CMSIS/Include;..\..\..\..\..\core;..\..\..\..\..\common;..\..\..\..\..\osal;..\..\..\..\..\class\cdc;..\..\..\..\..\class\hid;..\..\..\..\..\class\msc;..\..\..\..\..\class\hub;..\..\..\..\..\third_party\FreeRTOS-10.4\include;..\..\..\..\..\third_party\FreeRTOS-10.4\portable\GCC\ARM_CM7\r0p1 + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32h743xx.s + 2 + startup_stm32h743xx.s + + + + + Application/User/Core + + + main.c + 1 + ../Core/Src/main.c + + + stm32h7xx_it.c + 1 + ../Core/Src/stm32h7xx_it.c + + + stm32h7xx_hal_msp.c + 1 + ../Core/Src/stm32h7xx_hal_msp.c + + + usb_host.c + 1 + ..\..\..\..\usb_host.c + + + + + Drivers/STM32H7xx_HAL_Driver + + + stm32h7xx_hal_cortex.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c + + + stm32h7xx_hal_rcc.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c + + + stm32h7xx_hal_rcc_ex.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c + + + stm32h7xx_hal_flash.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c + + + stm32h7xx_hal_flash_ex.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c + + + stm32h7xx_hal_gpio.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c + + + stm32h7xx_hal_hsem.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c + + + stm32h7xx_hal_dma.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c + + + stm32h7xx_hal_dma_ex.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c + + + stm32h7xx_hal_mdma.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c + + + stm32h7xx_hal_pwr.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c + + + stm32h7xx_hal_pwr_ex.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c + + + stm32h7xx_hal.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c + + + stm32h7xx_hal_i2c.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c + + + stm32h7xx_hal_i2c_ex.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c + + + stm32h7xx_hal_exti.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c + + + stm32h7xx_hal_tim.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c + + + stm32h7xx_hal_tim_ex.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c + + + stm32h7xx_hal_uart.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c + + + stm32h7xx_hal_uart_ex.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c + + + stm32h7xx_hal_hcd.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + + + stm32h7xx_ll_usb.c + 1 + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c + + + + + Drivers/CMSIS + + + system_stm32h7xx.c + 1 + ../Core/Src/system_stm32h7xx.c + + + + + FreeRTOS + + + croutine.c + 1 + ..\..\..\..\..\third_party\FreeRTOS-10.4\croutine.c + + + event_groups.c + 1 + ..\..\..\..\..\third_party\FreeRTOS-10.4\event_groups.c + + + list.c + 1 + ..\..\..\..\..\third_party\FreeRTOS-10.4\list.c + + + queue.c + 1 + ..\..\..\..\..\third_party\FreeRTOS-10.4\queue.c + + + tasks.c + 1 + ..\..\..\..\..\third_party\FreeRTOS-10.4\tasks.c + + + timers.c + 1 + ..\..\..\..\..\third_party\FreeRTOS-10.4\timers.c + + + heap_4.c + 1 + ..\..\..\..\..\third_party\FreeRTOS-10.4\portable\MemMang\heap_4.c + + + port.c + 1 + ..\..\..\..\..\third_party\FreeRTOS-10.4\portable\GCC\ARM_CM7\r0p1\port.c + + + + + CherryUSB + + + usbh_core.c + 1 + ..\..\..\..\..\core\usbh_core.c + + + usb_osal_freertos.c + 1 + ..\..\..\..\..\osal\usb_osal_freertos.c + + + usb_workq.c + 1 + ..\..\..\..\..\osal\usb_workq.c + + + usbh_cdc_acm.c + 1 + ..\..\..\..\..\class\cdc\usbh_cdc_acm.c + + + usbh_hid.c + 1 + ..\..\..\..\..\class\hid\usbh_hid.c + + + usbh_msc.c + 1 + ..\..\..\..\..\class\msc\usbh_msc.c + + + usb_hc_dwc2.c + 1 + ..\..\..\..\..\port\dwc2\usb_hc_dwc2.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/demo/stm32/usb_host/stm32h743xih6/stm32h743xih6.ioc b/demo/stm32/usb_host/stm32h743xih6/stm32h743xih6.ioc new file mode 100644 index 00000000..f7e8b6be --- /dev/null +++ b/demo/stm32/usb_host/stm32h743xih6/stm32h743xih6.ioc @@ -0,0 +1,187 @@ +#MicroXplorer Configuration settings - do not modify +CORTEX_M7.CPU_DCache=Enabled +CORTEX_M7.CPU_ICache=Enabled +CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.Family=STM32H7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=DEBUG +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SYS +Mcu.IP5=USART1 +Mcu.IP6=USB_OTG_HS +Mcu.IPNb=7 +Mcu.Name=STM32H743XIHx +Mcu.Package=TFBGA240 +Mcu.Pin0=PA14 (JTCK/SWCLK) +Mcu.Pin1=PA13 (JTMS/SWDIO) +Mcu.Pin2=PA10 +Mcu.Pin3=PA9 +Mcu.Pin4=PH1-OSC_OUT (PH1) +Mcu.Pin5=PH0-OSC_IN (PH0) +Mcu.Pin6=PB15 +Mcu.Pin7=PB14 +Mcu.Pin8=VP_SYS_VS_Systick +Mcu.PinsNb=9 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32H743XIHx +MxCube.Version=6.2.0 +MxDb.Version=DB.6.0.20 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.OTG_HS_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA10.GPIOParameters=GPIO_Speed +PA10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA10.Locked=true +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA13\ (JTMS/SWDIO).Mode=Serial_Wire +PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO +PA14\ (JTCK/SWCLK).Mode=Serial_Wire +PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK +PA9.GPIOParameters=GPIO_Speed +PA9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA9.Locked=true +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB14.GPIOParameters=GPIO_Speed +PB14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB14.Mode=Host_FS +PB14.Signal=USB_OTG_HS_DM +PB15.GPIOParameters=GPIO_Speed +PB15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB15.Mode=Host_FS +PB15.Signal=USB_OTG_HS_DP +PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage=E\:\\Library\\STM32\\STM32Cube_FW_H7_V1.8.0 +ProjectManager.DefaultFWLocation=false +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32H743XIHx +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.9.1 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x1000 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=stm32h743xih6.ioc +ProjectManager.ProjectName=stm32h743xih6 +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x1000 +ProjectManager.TargetToolchain=MDK-ARM V5.27 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USB_HOST_Init-USB_HOST-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.ADCFreq_Value=50390625 +RCC.AHB12Freq_Value=200000000 +RCC.AHB4Freq_Value=200000000 +RCC.APB1Freq_Value=100000000 +RCC.APB2Freq_Value=100000000 +RCC.APB3Freq_Value=100000000 +RCC.APB4Freq_Value=100000000 +RCC.AXIClockFreq_Value=200000000 +RCC.CECFreq_Value=32000 +RCC.CKPERFreq_Value=64000000 +RCC.CortexFreq_Value=400000000 +RCC.CpuClockFreq_Value=400000000 +RCC.D1CPREFreq_Value=400000000 +RCC.D1PPRE=RCC_APB3_DIV2 +RCC.D2PPRE1=RCC_APB1_DIV2 +RCC.D2PPRE2=RCC_APB2_DIV2 +RCC.D3PPRE=RCC_APB4_DIV2 +RCC.DFSDMACLkFreq_Value=400000000 +RCC.DFSDMFreq_Value=100000000 +RCC.DIVM1=5 +RCC.DIVM3=25 +RCC.DIVN1=160 +RCC.DIVN3=240 +RCC.DIVP1Freq_Value=400000000 +RCC.DIVP2Freq_Value=50390625 +RCC.DIVP3Freq_Value=120000000 +RCC.DIVQ1Freq_Value=400000000 +RCC.DIVQ2Freq_Value=50390625 +RCC.DIVQ3=5 +RCC.DIVQ3Freq_Value=48000000 +RCC.DIVR1Freq_Value=400000000 +RCC.DIVR2Freq_Value=50390625 +RCC.DIVR3Freq_Value=120000000 +RCC.FDCANFreq_Value=400000000 +RCC.FMCFreq_Value=200000000 +RCC.FamilyName=M +RCC.HCLK3ClockFreq_Value=200000000 +RCC.HCLKFreq_Value=200000000 +RCC.HPRE=RCC_HCLK_DIV2 +RCC.HRTIMFreq_Value=200000000 +RCC.I2C123Freq_Value=100000000 +RCC.I2C4Freq_Value=100000000 +RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +RCC.LPTIM1Freq_Value=100000000 +RCC.LPTIM2Freq_Value=100000000 +RCC.LPTIM345Freq_Value=100000000 +RCC.LPUART1Freq_Value=100000000 +RCC.LTDCFreq_Value=120000000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=400000000 +RCC.QSPIFreq_Value=200000000 +RCC.RNGFreq_Value=48000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=400000000 +RCC.SAI23Freq_Value=400000000 +RCC.SAI4AFreq_Value=400000000 +RCC.SAI4BFreq_Value=400000000 +RCC.SDMMCFreq_Value=400000000 +RCC.SPDIFRXFreq_Value=400000000 +RCC.SPI123Freq_Value=400000000 +RCC.SPI45Freq_Value=100000000 +RCC.SPI6Freq_Value=100000000 +RCC.SWPMI1Freq_Value=100000000 +RCC.SYSCLKFreq_VALUE=400000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.Tim1OutputFreq_Value=200000000 +RCC.Tim2OutputFreq_Value=200000000 +RCC.TraceFreq_Value=400000000 +RCC.USART16Freq_Value=100000000 +RCC.USART234578Freq_Value=100000000 +RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3 +RCC.USBFreq_Value=48000000 +RCC.VCO1OutputFreq_Value=800000000 +RCC.VCO2OutputFreq_Value=100781250 +RCC.VCO3OutputFreq_Value=240000000 +RCC.VCOInput1Freq_Value=5000000 +RCC.VCOInput2Freq_Value=781250 +RCC.VCOInput3Freq_Value=1000000 +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC +USB_OTG_HS.IPParameters=VirtualMode-Host_FS,dma_enable-Host_FS +USB_OTG_HS.VirtualMode-Host_FS=Host_FS +USB_OTG_HS.dma_enable-Host_FS=ENABLE +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom -- cgit v1.3.1