opensbi.git, branch v0.6

include: Bump-up version to 0.6

2020-02-24T05:57:57Z

This patch updates OpenSBI version to 0.6 as part of release preparation. Signed-off-by: Anup Patel

lib: Simplify the for-loop in sbi_ipi_send_many()

2020-02-24T03:40:04Z

We don't need to separately call sbi_ipi_send() for current HART in sbi_ipi_send_many(). Instead, we can simplify the for-loop in sbi_ipi_send_many() and call sbi_ipi_send() for all HARTs in the for-loop itself. Signed-off-by: Anup Patel Reviewed-by: Bin Meng

lib: Use available hart mask for correct hbase value

2020-02-22T04:36:51Z

As per the latest SBI specification, all online harts should receive IPI if hbase is set to -1. Set the target mask to all available hart mask if hbase is -1. Signed-off-by: Atish Patra Reviewed-by: Anup Patel

lib: Fix typo in atomic exchange functions

2020-02-22T04:34:38Z

There is a typo in atomic operations code which prevents the usage of riscv atomic instructions even if it is supported. Fix the typo. Signed-off-by: Atish Patra Reviewed-by: Anup Patel

platform: qemu: virt: Correct the typo in config.mk

2020-02-19T11:23:42Z

It should be "aligned". Signed-off-by: Bin Meng Reviewed-by: Anup Patel

platform: sifive: fu540: Add 32-bit specific fdt/payload addresses

2020-02-19T11:22:07Z

For testing 32-bit SiFive specific drivers with QEMU riscv32, add 32-bit specific FW_JUMP_FDT_ADDR and FW_PAYLOAD_OFFSET. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: Print interrupt and exception delegation in boot prints

2020-02-19T04:28:48Z

We print MIDELEG and MEDELEG CSRs as part of boot prints so that boot log shows the interrupts and exceptions delegated to S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Atish Patra

lib: Don't check MIDELEG and MEDELEG at end of delegate_traps()

2020-02-19T04:28:45Z

The MIDELEG and MEDELEG CSR checks at end of delegate_traps() were added for initial bring-up on SiFive Unleashed and QEMU. These checks are not required any more and in-future these checks can cause failures because some of the MIDELEG/MEDELEG bits will be hard-wired to 0 or 1. For related discussion, refer github issue: https://github.com/riscv/opensbi/issues/157 Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Atish Patra

lib: utils: htif: Fix 32-bit build

2020-02-18T05:00:16Z

When building 32-bit OpenSBI images, we get: lib/utils/sys/htif.c: In function '__check_fromhost': lib/utils/sys/htif.c:12:31: error: left shift count >= width of type [-Werror=shift-count-overflow] #define HTIF_DATA_MASK ((1UL << HTIF_DATA_BITS) - 1) ^~ Fixes: c2f23cc6edd7 ("platform: Add Spike initial support") Signed-off-by: Bin Meng Reviewed-by: Anup Patel

Revert "lib: Use __builtin_ctzl() in pmp_get()"

2020-02-18T03:58:33Z

This reverts commit 897b8fbdd92fcfad194417d348b8dad16ab0e17a. We are seeing compile errors using newlib based GCC cross-toolchain so we restore back old ctz() implementation. Signed-off-by: Anup Patel