opensbi.git, branch v0.8

include: Bump-up version to 0.8

2020-06-20T06:27:24Z

This patch updates OpenSBI version to 0.8 as part of release preparation. Signed-off-by: Anup Patel

lib: Don't return any invalid error from SBI ecall

2020-06-20T05:06:13Z

We should only return valid error codes from SBI ecalls as defined by the RISC-V SBI spec. To achieve this: 1. We use SBI_Exxxx defines for OpenSBI internal errors with error values starting from -1000 2. We use SBI_ERR_xxxx defines for errors defined by SBI spec 3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines which are semantically same 4. We throw a error print and force return error code to SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid error code being returned to S-mode Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Fix 32/64 bits variable compatibility

2020-06-20T03:17:11Z

On RV64,"unsigned long" is 64bit and "unsigned int" is 32bit. So in function "pmp_get" and "pmp_set", if "pmpcfg_shift >= 32", "0xff << pmpcfg_shift" will go beyond "unsigned int" width. This patch tries to fix this issue. In function 'pmp_get': cfgmask = (0xff << pmpcfg_shift); --> cfgmask = (0xffUL << pmpcfg_shift); In function 'pmp_set': cfgmask = ~(0xff << pmpcfg_shift); --> cfgmask = ~(0xffUL << pmpcfg_shift); Signed-off-by: Liush Reviewed-by: Anup Patel

platform: Add support for Shakti C-class SoC from IIT-M

2020-06-19T03:51:46Z

C-Class is a member of the SHAKTI family of processors from Indian Institute of Technology - Madras(IIT-M). It is an extremely configurable and commercial-grade 5-stage in-order core supporting the standard RV64GCSUN ISA extensions. https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md We add OpenSBI support for Shakti C-class SoC. Signed-off-by: Vijai Kumar K Reviewed-by: Anup Patel

lib: Fix the SBI_HART_HAS_MCOUNTEREN feature check

2020-06-18T03:28:13Z

Signed-off-by: Alistair Francis Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: Don't print delegation CSRs if there is no S-Mode

2020-06-18T03:26:54Z

If the platform doesn't support S-Mode don't print the delegation registers. Signed-off-by: Alistair Francis Reviewed-by: Atish Patra Reviewed-by: Anup Patel

platform: Update Nuclei ux600 platform support

2020-06-17T15:36:40Z

Changes are made to support our FPGA evaluation board, it has DDR memory(0xA0000000-0xB0000000). * Adapt the config.mk to match FPGA evaluation board DDR memory address * Since the RISC-V CPU core frequency of FPGA might change, so we use the fixed TIMER frequency to measure the real CPU core frequency. * And the UART baudrate has to set to 57600bps for Nuclei FPGA evaluation board when CPU core frequency is about 8MHz, otherwise the UART input will not work correctly. Signed-off-by: Huaqi Fang <578567190@qq.com> Reviewed-by: Anup Patel

platform/lib: Allow the OS to map the regions that are protected by PMP

2020-06-15T03:55:44Z

This is achieved by removing the 'no-map' property from the 'reserved-memory' node when PMP is present, otherwise we keep it as it offers a small protection if the OS does not map this region at all. A new callback in platform_override is introduced and allows to fixup the device-tree. It is used here to override this new default behaviour on SiFive Fu540 platforms that has an erratum that prevents S-mode software to access a PMP protected region using 1GB page table mapping. If PMP is present, telling the OS not to map the reserved regions does not add much protection since it only avoids access to regions that are already protected by PMP. But by not allowing the OS to map those regions, it creates holes in the OS system memory map and prevents the use of hugepages which would generate, among other benefits, less TLB miss. Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va()

2020-06-15T03:54:27Z

The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va() functions are swapped so we fix it. Currently, we did not face any issues because QEMU does a full TLB flush for all HFENCE instructions. We also improve documentation of HFENCE.GVMA and HFENCE.VVMA instruction encoding. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

platform: Add AE350 cache control SBIs

2020-06-10T03:58:52Z

This patch contains the following AE350 specific SBIs: - get mcache_ctl status - get mmisc_ctl status - set mcache_ctl status - set mmisc_ctl status - I-cache operation - D-cache operation - enable/disable L1-I-cache prefetch - enable/disable L1-D-cache prefetch - enable/disable non-blocking load store - enable/disable write-around Signed-off-by: Nylon Chen Reviewed-by: Anup Patel Reviewed-by: Atish Patra