opensbi.git, branch v1.1

include: Bump-up version to 1.1

2022-06-25T03:42:10Z

This patch updates OpenSBI version to 1.1 as part of release preparation. Signed-off-by: Anup Patel

lib: pmu: allow to use the highest available counter

2022-06-25T03:14:20Z

OpenSBI explicitly assumes that there is no pmu hardware counter with index 1: hardware uses that bit for TM control. So OpenSBI filters out that index in sanity checks. However OpenSBI also excludes that counter when reports total amount of hardware counters to Linux. As a result, Linux uses incomplete counters mask excluding the highest available counter. Return accurate number of counters, update the firmware counter starting index, fix range checks that include num_hw_ctrs. The simple test is to make sure that there is no counter multiplexing in the following command: $ perf stat -e \ r8000000000000000,r8000000000000001,r8000000000000002,r8000000000000003, \ r8000000000000004,r8000000000000005,r8000000000000006,r8000000000000007, \ r8000000000000008,r8000000000000009,r800000000000000a,r800000000000000b, \ r800000000000000c,r800000000000000d,r800000000000000e,r800000000000000f \ ls Note that 16 firmware events with 16 counters won't require multiplexing. Signed-off-by: Sergey Matyukevich Signed-off-by: Atish Patra Reviewed-by: Atish Patra

include: sbi: Change spec version to 1.0

2022-06-24T03:24:59Z

Now that SBI v1.0 specification is ratified, we change spec verion implemented by OpenSBI to v1.0. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: utils/timer: Remove Allwinner D1 CLINT compatibles

2022-06-22T05:25:37Z

The allwinner,sun20i-d1-clint compatible string is not documented in any official binding, so it should not be used by drivers. The MSWI in the D1 CLINT is compatible with the ACLINT specification, so it can take advantage of generic driver support. However, that is only possible if the MSWI and MTIMER are split into separate DT nodes. This means the final binding for this device is likely to be incompatible with what is implemented here. Remove this compatible string from the driver to prevent it from appearing in a stable version and causing future issues. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: irqchip/plic: fix typo in plic_warm_irqchip_init

2022-06-22T05:25:27Z

The second invocation of plic_context_init() incorrectly calls the function with m_cntx_id instead of s_cntx_id. This breaks systems which only have 1 external interrupt per hart. Fixes: 8c362e7 ("lib: irqchip/plic: Factor out a context init function") Signed-off-by: Jan Remes Reviewed-by: Anup Patel Reviewed-by: Samuel Holland

lib: utils/timer: Add a separate compatible for the D1 CLINT

2022-06-21T03:50:59Z

The CLINT in the Allwinner D1 SoC apparently does not support 64-bit MMIO access. A property was added to support this quirk (and that property was copied to the ACLINT MTIMER code). However, since this difference in behavior makes the D1 CLINT incompatible with the SiFive CLINT's programming interface, a better solution is to use a separate compatible string. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bits

2022-06-21T03:14:45Z

Based on architecture review committee feedback, the [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are removed in the latest AIA draft v0.3.0 specification. (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31) These CSRs were mostly for software convenience and software can always use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt file bits. We update the IMSIC programming as-per above to match the latest AIA draft specification. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Fix tval and tinst for sbi_get_insn()

2022-06-21T03:01:56Z

We should not change trap->tval to mepc because mtval already points to the faulting portion of the emulated instruction fetch, which is also what stval is expected to be. In addition, htinst is only allowed to be zero for instruction access faults or page faults, and is only allowed to be zero or a psuedoinstruction for instruction guest-page faults. Fix trap->tinst for these cases. Signed-off-by: dramforever Reviewed-by: Anup Patel

lib: sbi: Fixup tinst for exceptions in sbi_misaligned_*()

2022-06-21T03:01:14Z

If there is an exception while emulating a misaligned load/store, fixup uptrap.tinst before redirecting. Otherwise, HS-mode software may receive an htinst describing the lbu/sb instruction that faulted during emulation[1]. [1]: https://github.com/riscv-software-src/opensbi/issues/258 Signed-off-by: dramforever Reviewed-by: Anup Patel

include: sbi: Add mtinst/htinst psuedoinstructions

2022-06-21T03:01:04Z

Add psuedoinstruction encodings written to mtinst/htinst for faults caused by implicit memory access for VS-stage address translation Signed-off-by: dramforever Reviewed-by: Anup Patel