opensbi.git, branch v1.2

include: Bump-up version to 1.2

2022-12-24T06:06:49Z

This patch updates OpenSBI version to 1.2 as part of release preparation. Signed-off-by: Anup Patel

docs: pmu: Update the pmu doc with removal of mcountinhbit restriction

2022-12-24T05:37:14Z

Since commit b28f070, it is possible for platforms to run perf monitoring even if mcountinhibit is not supported. Sampling still won't be possible though as it requires sscofpmf extension. Update the docs to remove the restriction. Signed-off-by: Atish Patra Reviewed-by: Anup Patel

docs: pmu: update a reference to a deprecated property name

2022-12-24T05:36:04Z

event-to-mhpmevent was deprecated and replaced by riscv,event-to-mhpmevent, but a reference remains to the old name. Replace it with the new one. Signed-off-by: Conor Dooley Reviewed-by: Atish Patra Reviewed-by: Anup Patel

docs: pmu: fix binding example

2022-12-24T05:35:09Z

The first PMU binding example does not terminate properties with a ;, which is invalid. Noticed while converting the binding to yaml. Signed-off-by: Conor Dooley Reviewed-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible

2022-12-17T05:31:06Z

As we already added the quirk for lacking mtime register to MTIMER driver, add T-Head C9xx CLINT compatible to it and wire the quirk. Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel

lib: utils/timer: mtimer: add a quirk for lacking mtime register

2022-12-17T05:31:03Z

T-Head developers surely have a different understanding of time CSR and CLINT's mtime register with SiFive ones, that they did not implement the mtime register at all -- as shown in openC906 source code, their time CSR value is just exposed at the top of their processor IP block and expects an external continous counter, which makes it not overrideable, and thus mtime register is not implemented, even not for reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS extended CSR, these systems still rely on the mtimecmp registers to generate timer interrupts. This makes it necessary to implement T-Head C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing reading mtime register and falls back to default code that reads time CSR. Add a quirk into MTIMER driver, which represents a mtime register is lacking and time CSR value should be used instead. Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel

lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible

2022-12-17T05:31:00Z

Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the MSWI part is compliant. Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing the same codepath with SiFive CLINT. Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

2022-12-17T03:33:30Z

Currently the context save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers

2022-12-17T03:32:40Z

plic->num_src holds the number of interrupt sources without interrupt source 0 but the interrupt enable register includes a bit for the interrupt source 0 in the first word. Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers") Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Samuel Holland

lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()

2022-12-17T03:30:35Z

The number of interrupt enable register in words was once correct, but was wrongly changed to have an off-by-one error since commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function"). Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function") Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Samuel Holland