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<title>opensbi.git/docs/platform, branch v1.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/docs/platform?h=v1.1</id>
<link rel='self' href='http://cgit.235523.xyz/opensbi.git/atom/docs/platform?h=v1.1'/>
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<updated>2022-06-21T03:50:59Z</updated>
<entry>
<title>lib: utils/timer: Add a separate compatible for the D1 CLINT</title>
<updated>2022-06-21T03:50:59Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-10-20T01:58:38Z</published>
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<id>urn:sha1:7738345396fbbae543a5af14fbc965d9163c12a0</id>
<content type='text'>
The CLINT in the Allwinner D1 SoC apparently does not support 64-bit
MMIO access. A property was added to support this quirk (and that
property was copied to the ACLINT MTIMER code). However, since this
difference in behavior makes the D1 CLINT incompatible with the SiFive
CLINT's programming interface, a better solution is to use a separate
compatible string.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>docs/platform: spike: Enhance Spike examples</title>
<updated>2021-12-11T10:54:39Z</updated>
<author>
<name>Tsukasa OI</name>
<email>research_trasio@irq.a4lg.com</email>
</author>
<published>2021-12-03T01:13:56Z</published>
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<id>urn:sha1:66fbcc03df0444bb6ce2286d3605cbc13b361cb1</id>
<content type='text'>
This commit makes Spike usable as QEMU (in fact, those are based on
QEMU examples).

Signed-off-by: Tsukasa OI &lt;research_trasio@irq.a4lg.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Automatically delegate T-HEAD PLIC access</title>
<updated>2021-10-21T04:36:00Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-10-18T05:33:50Z</published>
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<id>urn:sha1:78c2b19218bd62653b9fb31623a42ced45f38ea6</id>
<content type='text'>
The T-HEAD PLIC implementation requires setting a delegation bit
to allow access from S-mode. Now that the T-HEAD PLIC has its own
compatible string, set this bit automatically from the PLIC driver,
instead of reaching into the PLIC's MMIO space from another driver.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs/platform: thead-c9xx: Remove FW_PIC=y</title>
<updated>2021-07-06T05:20:44Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-07-03T15:09:29Z</published>
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<id>urn:sha1:197e08941bd394b6b88ad07c5a3adfe67f5b3b10</id>
<content type='text'>
FW_PIC is on by default. Hence no need to explicitly require it.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs/platform: andes-ae350: Fix missing spaces</title>
<updated>2021-06-11T05:48:07Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-06-04T15:35:43Z</published>
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<id>urn:sha1:b32fac4b65aabcd5fb555a87fcd94b4f2e297357</id>
<content type='text'>
Fix several places in the docmentation that are missing spaces.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs: debugging OpenSBI</title>
<updated>2021-06-02T11:34:07Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2021-05-28T16:22:14Z</published>
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<id>urn:sha1:d9ba6536d307f05a838e7c96cd20b0b7e43ec886</id>
<content type='text'>
Describe how to debug OpenSBI on QEMU with GDB.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs: platform: Describe sifive_fu540 as supported generic platform</title>
<updated>2021-05-06T08:53:38Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-04-29T10:16:08Z</published>
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<id>urn:sha1:d4177e72179e7898b79b7316deeea7af3866871f</id>
<content type='text'>
The upstream U-Boot/QEMU have been using generic platform for SiFive
HiFive Unleashed board for some time. Let's document sifive_fu540 as
one of the supported targets for "generic" platform.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs: platform: Sort platform names</title>
<updated>2021-05-06T08:52:34Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-04-29T10:16:07Z</published>
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<id>urn:sha1:552f53f36088a25e2c2a51f41c13e7edae6c32e3</id>
<content type='text'>
Let's sort the platform names in alphabetical order.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs/platform: sifive_fu540: Update U-Boot defconfig name</title>
<updated>2021-04-29T09:41:24Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-04-21T04:20:04Z</published>
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<id>urn:sha1:632e27bb91b824974b88dd46f8419729d7f9825d</id>
<content type='text'>
With latest U-Boot upstream (v2021.07 in development), the defconfig
name has been changed to sifive_unleashed_defconfig. Update the doc.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs: generic: Add T-HEAD C9xx series processors</title>
<updated>2021-04-28T10:42:02Z</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2021-04-27T06:47:53Z</published>
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<id>urn:sha1:6d1642f85693395e19b9b7087f216a2c02e4c81e</id>
<content type='text'>
Add description and dts examples for T-HEAD C9xx platforms.

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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