opensbi.git/docs/pmu_support.md, branch master

docs: pmu_support: fix example typos

2025-04-14T11:55:54Z

The (event ID & "second column mask") should equal the "first column match value". Modify the example to fit the description. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Samuel Holland Link: https://lore.kernel.org/r/20250324043943.2513070-1-ycliang@andestech.com Signed-off-by: Anup Patel

docs: pmu: Add Andes PMU node example

2023-12-06T12:51:25Z

Add PMU node example for event index to counter index mapping and selector value translation of Andes' CPUs. Currently, there are 4 HPM counters that can be used to monitor all of the events for each hart. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Locus Wei-Han Chen Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Anup Patel Reviewed-by: Lad Prabhakar

docs: pmu: Update the pmu doc with removal of mcountinhbit restriction

2022-12-24T05:37:14Z

Since commit b28f070, it is possible for platforms to run perf monitoring even if mcountinhibit is not supported. Sampling still won't be possible though as it requires sscofpmf extension. Update the docs to remove the restriction. Signed-off-by: Atish Patra Reviewed-by: Anup Patel

docs: pmu: update a reference to a deprecated property name

2022-12-24T05:36:04Z

event-to-mhpmevent was deprecated and replaced by riscv,event-to-mhpmevent, but a reference remains to the old name. Replace it with the new one. Signed-off-by: Conor Dooley Reviewed-by: Atish Patra Reviewed-by: Anup Patel

docs: pmu: fix binding example

2022-12-24T05:35:09Z

The first PMU binding example does not terminate properties with a ;, which is invalid. Noticed while converting the binding to yaml. Signed-off-by: Conor Dooley Reviewed-by: Bin Meng Reviewed-by: Anup Patel

docs: Fix some typos

2022-10-13T03:58:54Z

We fix few typos in documentation. Signed-off-by: zhangdongdong Reviewed-by: Andrew Jones Reviewed-by: Xiang W Reviewed-by: Anup Patel

docs: pmu: extend bindings example for Unmatched

2022-09-13T11:12:10Z

Extend example for Unmatched board to provide SBI PMU bindings for generalized and cache event's where they are applicable. Signed-off-by: Nikita Shubin Reviewed-by: Anup Patel

docs: pmu: fix Unmatched example typo

2022-09-13T11:12:03Z

bitmap for MHPMCOUNTERx should be 0x18 and not 0x0c, we check against SBI_PMU_FIXED_CTR_MASK which assumes than first 3 bits are dedicated to mcycle, mtime and minstret, u74 has 2 hardware counters. Reported-by: Zhang Xin Signed-off-by: Nikita Shubin Reviewed-by: Anup Patel

docs: pmu: Improve the PMU DT bindings

2022-04-28T06:10:15Z

The current DT binding description is misleading and confusing. Clarify the text and provide more examples. Signed-off-by: Atish Patra Reviewed-by: Anup Patel

lib: pmu: support the event ID encoded by a bitmap.

2021-12-03T04:07:03Z

RISC-V privilege specification does not specify how to encode the event ID. Therefore, each platform is allowed to customize its own encoding rule. The common encoding methods are as follow, directly assigning a number to an event, or every bit in the mphmevent CSR controls one specified event or mixes the above two methods. To enable OpenSBI to support the above three encoding methods simultaneously, this patch repurpose the dt property "riscv,raw-event-to-mhpmcounters". The "riscv,raw-event-to-mhpmcounters" will describes the one or multiple raw events that could be counted by a set of counters. But, the column number of "riscv,raw-event-to-mhpmcounters" is extended from 2 to 3. The 1st column (64bit) is the ID of the raw events. The 2nd column (64bit) represents a select_mask now to represent the bits used for event ID encoding. If a platform directly encodes each raw PMU event as a unique ID, the value of select_mask will be 0xffffffff_ffffffff. Signed-off-by: Vincent Chen Signed-off-by: Atish Patra Reviewed-by: Anup Patel