opensbi.git/docs, branch v1.1

lib: utils/timer: Add a separate compatible for the D1 CLINT

2022-06-21T03:50:59Z

The CLINT in the Allwinner D1 SoC apparently does not support 64-bit MMIO access. A property was added to support this quirk (and that property was copied to the ACLINT MTIMER code). However, since this difference in behavior makes the D1 CLINT incompatible with the SiFive CLINT's programming interface, a better solution is to use a separate compatible string. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

docs: pmu: Improve the PMU DT bindings

2022-04-28T06:10:15Z

The current DT binding description is misleading and confusing. Clarify the text and provide more examples. Signed-off-by: Atish Patra Reviewed-by: Anup Patel

docs/platform: spike: Enhance Spike examples

2021-12-11T10:54:39Z

This commit makes Spike usable as QEMU (in fact, those are based on QEMU examples). Signed-off-by: Tsukasa OI Reviewed-by: Anup Patel

lib: pmu: support the event ID encoded by a bitmap.

2021-12-03T04:07:03Z

RISC-V privilege specification does not specify how to encode the event ID. Therefore, each platform is allowed to customize its own encoding rule. The common encoding methods are as follow, directly assigning a number to an event, or every bit in the mphmevent CSR controls one specified event or mixes the above two methods. To enable OpenSBI to support the above three encoding methods simultaneously, this patch repurpose the dt property "riscv,raw-event-to-mhpmcounters". The "riscv,raw-event-to-mhpmcounters" will describes the one or multiple raw events that could be counted by a set of counters. But, the column number of "riscv,raw-event-to-mhpmcounters" is extended from 2 to 3. The 1st column (64bit) is the ID of the raw events. The 2nd column (64bit) represents a select_mask now to represent the bits used for event ID encoding. If a platform directly encodes each raw PMU event as a unique ID, the value of select_mask will be 0xffffffff_ffffffff. Signed-off-by: Vincent Chen Signed-off-by: Atish Patra Reviewed-by: Anup Patel

lib: utils: Rename the prefix in PMU DT properties

2021-11-11T12:24:46Z

As per the DT schema rules, the prefix should be vendor. As the PMU properties are generic for all vendors, change the prefix to riscv instead of pmu. Reviewed-by: Anup Patel Reviewed-by: Bin Meng Signed-off-by: Atish Patra

lib: utils/irqchip: Automatically delegate T-HEAD PLIC access

2021-10-21T04:36:00Z

The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver. Signed-off-by: Samuel Holland Reviewed-by: Bin Meng Reviewed-by: Anup Patel

docs: Document FW_PIC compile time option

2021-07-17T12:13:37Z

FW_PIC=y is on by default, but the doc is missing when this was introduced. Add some description for it. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

docs: Document parameters passed to firmware and alignment requirement

2021-07-17T12:00:48Z

This updates documentation to describe parameters passed to firmware from previous booting stage, and corresponding address alignment requirement. This also fixes a typo in fw_dynamic.md (it's => its). Signed-off-by: Bin Meng Reviewed-by: Anup Patel

docs: Make visible in the rendered platform guide

2021-07-11T06:28:31Z

At present in the rendered platform guide, all instances of are missing. Use < and > to replace <> to make them visible. Signed-off-by: Bin Meng Reviewed-by: Xiang W Reviewed-by: Anup Patel

docs: Correct a typo in platform_guide.md

2021-07-11T06:25:55Z

It's riscv-pk, not riskv-pk. Signed-off-by: Bin Meng Reviewed-by: Xiang W Reviewed-by: Anup Patel