opensbi.git/firmware/fw_base.S, branch release-1.3.x

firmware: Fix find hart index

2023-06-21T04:50:51Z

After the loop to find the hartid is launched, assigning -1 to index will fail in the subsequent compare instruction bge. Fix This. Signed-off-by: Xiang W Reviewed-by: Anup Patel

platform: Allow platforms to specify heap size

2023-06-05T10:15:33Z

We extend struct sbi_platform and struct sbi_scratch to allow platforms specify the heap size to the OpenSBI firmwares. The OpenSBI firmwares will use this information to determine the location of heap and provide heap base address in per-HART scratch space. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones

firmware: Change to use positive offset to access relocation entries

2023-04-17T03:25:55Z

The codes currently skip the very first relocation entry, but later reference the elements in the relocation entry using minus offsets. Change to use positive offsets so that there is no need to skip the first relocation entry. Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Xiang W

firmware: Optimize loading relocation type

2023-04-17T03:25:49Z

't5' already contains relocation type so don't bother reloading it. Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Xiang W

lib: sbi_hart: clear mip csr during hart init

2023-04-06T13:22:03Z

If mip.SEIP bit is not cleared then on HiFive Unmatched board it causes spurious external interrupts. This breaks the boot up of HiFive Unmatched board. Hence it is required to bring the mip CSR to a known state during hart init and avoid spurious interrupts. Fixes: d9e7368 ("firmware: Not to clear all the MIP") Signed-off-by: Mayuresh Chitale Reviewed-by: Anup Patel

firmware: Not to clear all the MIP

2023-02-08T05:09:20Z

In generic behavior of QEMU, if the pending bits of PLIC are still set and we clear the SEIP, the QEMU may not set the SEIP back immediately and the interrupt may not be handled anymore until the new interrupts arrived and QEMU set the SEIP back which is a generic behavior in QEMU. Signed-off-by: Nick Hu Signed-off-by: Jim Shu Reviewed-by: Anup Patel

firmware: Fix fw_rw_offset computation in fw_base.S

2023-01-27T03:09:49Z

It seems BFD just does totally nonsensical things for SHN_ABS symbols when producing position-independent outputs (both -pie and -shared) for various historical reasons, and so SHN_ABS symbols are still subject to relocation as far as BFD is concerned (except AArch64, which fixes it in limited cases that don’t apply here...). The above affects the _fw_rw_offset provided through fw_base.ldS linker script which results in OpenSBI firmware failing to boot when loaded at an address different from FW_TEXT_START. Fixes: c10e3fe5f9a1 ("firmware: Add RW section offset in scratch") Signed-off-by: Jessica Clarke Reported-by: Lad Prabhakar Tested-by: Lad Prabhakar Tested-by: Anup Patel Signed-off-by: Anup Patel

firmware: Add RW section offset in scratch

2023-01-23T04:36:14Z

Add the RW section offset, provided by _fw_rw_offset symbol, to the scratch structure. This will be used to program separate pmp entry for RW section. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel

firmware: Minor optimization for relocate

2022-12-05T05:17:38Z

The t3 register stores the address of _load_end. If relocation is not required, it is unnecessary to calculate the address of _load_end. This can reduce the operation time of two instructions. Signed-off-by: Dongdong Zhang Reviewed-by: Bin Meng Reviewed-by: Anup Patel

firmware: Fix code for accessing hart_count and stack_size

2022-03-27T03:23:27Z

lwu exists under the current rv64 and should also exist under the rv128 in the future, so I modified the conditions of conditional compilation so that it can adapt to the future situation Signed-off-by: Xiang W Reviewed-by: Anup Patel