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<title>opensbi.git/firmware/fw_base.S, branch v1.4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/firmware/fw_base.S?h=v1.4</id>
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<updated>2023-11-16T10:49:42Z</updated>
<entry>
<title>firmware: fw_base.S: Fix boot hart status synchronization</title>
<updated>2023-11-16T10:49:42Z</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2023-10-19T09:27:34Z</published>
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<id>urn:sha1:fccdf41d32877eca0cef3789d12a197cba73c2e2</id>
<content type='text'>
It's wrong to put the fence after setting the boot status flag because
all relocation operations must be finished before setting the status
flag. So, this fence must be put before the setting status flag, and
there is no use in putting a fence between _start_warm and setting
status flag.

Also, nop can't delay other harts too much, so use div instead, just
like Linux cpu_relax. Current opensbi force enables “M” Standard
Extension, and mul instructions have been used in the fw_base.S.

After the above two fixes, the boot hart index param of the
fw_dynamic_info could be guaranteed properly for all platforms.

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
Signed-off-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: Remove handling of R_RISCV_{32,64}</title>
<updated>2023-10-06T03:51:23Z</updated>
<author>
<name>Vivian Wang</name>
<email>dramforever@live.com</email>
</author>
<published>2023-09-17T17:52:50Z</published>
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<id>urn:sha1:2a6d72534d44c39e1de0614970a0dad97b1c41ba</id>
<content type='text'>
Since everything is statically linked, we won't actually have
R_RISCV_{32,64} relocations. No need to handle these.

Fixes: 0f20e8adcf42 ("firmware: Support position independent execution")
Signed-off-by: Vivian Wang &lt;dramforever@live.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>fw_base.S: Fix assembler error with clang 16+</title>
<updated>2023-08-06T05:36:02Z</updated>
<author>
<name>Mitchell Horne</name>
<email>mhorne@freebsd.org</email>
</author>
<published>2023-08-06T05:15:36Z</published>
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<id>urn:sha1:94197a8c49751eabe73ff2849fce183ac8ead3fd</id>
<content type='text'>
Attempting to build OpenSBI with clang 16 and the following command:

   $ make LLVM=1 PLATFORM=generic

Results in the following error:

    AS        platform/generic/firmware/fw_dynamic.o
   /tmp/fw_dynamic-d000a6.s:429:9: error: symbol '_fw_start' can not be undefined in a subtraction expression
    .dword _fw_rw_start - _fw_start

Work around this issue by eliminating the __fw_rw_offset variable and
performing the offset calculation at run-time instead. This takes
advantage of the fact that the a4 register contains the value of
_fw_start.

Signed-off-by: Mitchell Horne &lt;mhorne@FreeBSD.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: Fix find hart index</title>
<updated>2023-06-21T04:50:51Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2023-06-16T07:03:51Z</published>
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<id>urn:sha1:d64942f0e4fe63a248e7ba3dd7ff4dec02954134</id>
<content type='text'>
After the loop to find the hartid is launched, assigning -1 to
index will fail in the subsequent compare instruction bge. Fix
This.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: Allow platforms to specify heap size</title>
<updated>2023-06-05T10:15:33Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-17T05:58:03Z</published>
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<id>urn:sha1:5cf9a540164a018a31a679578a27eb964af0340d</id>
<content type='text'>
We extend struct sbi_platform and struct sbi_scratch to allow platforms
specify the heap size to the OpenSBI firmwares. The OpenSBI firmwares
will use this information to determine the location of heap and provide
heap base address in per-HART scratch space.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>firmware: Change to use positive offset to access relocation entries</title>
<updated>2023-04-17T03:25:55Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2023-04-04T04:46:01Z</published>
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<id>urn:sha1:e41dbb507c422c52cf93228ca7157394d49ca9fe</id>
<content type='text'>
The codes currently skip the very first relocation entry, but later
reference the elements in the relocation entry using minus offsets.

Change to use positive offsets so that there is no need to skip the
first relocation entry.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>firmware: Optimize loading relocation type</title>
<updated>2023-04-17T03:25:49Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2023-04-04T04:46:00Z</published>
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<id>urn:sha1:f692289ed42882567491c35700a1feb64ba540b5</id>
<content type='text'>
't5' already contains relocation type so don't bother reloading it.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi_hart: clear mip csr during hart init</title>
<updated>2023-04-06T13:22:03Z</updated>
<author>
<name>Mayuresh Chitale</name>
<email>mchitale@ventanamicro.com</email>
</author>
<published>2023-03-25T16:50:47Z</published>
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<id>urn:sha1:8e90259da8b4b5bc6c934506cc4302578d44dbc2</id>
<content type='text'>
If mip.SEIP bit is not cleared then on HiFive Unmatched board it causes
spurious external interrupts. This breaks the boot up of HiFive Unmatched
board. Hence it is required to bring the mip CSR to a known state during
hart init and avoid spurious interrupts.

Fixes: d9e7368 ("firmware: Not to clear all the MIP")
Signed-off-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: Not to clear all the MIP</title>
<updated>2023-02-08T05:09:20Z</updated>
<author>
<name>Nick Hu</name>
<email>nick.hu@sifive.com</email>
</author>
<published>2023-01-17T08:14:27Z</published>
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<id>urn:sha1:8050081f68b2b66f8937b15a6753ec6408c2fdee</id>
<content type='text'>
In generic behavior of QEMU, if the pending bits of PLIC are still set and
we clear the SEIP, the QEMU may not set the SEIP back immediately and the
interrupt may not be handled anymore until the new interrupts arrived and
QEMU set the SEIP back which is a generic behavior in QEMU.

Signed-off-by: Nick Hu &lt;nick.hu@sifive.com&gt;
Signed-off-by: Jim Shu &lt;jim.shu@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: Fix fw_rw_offset computation in fw_base.S</title>
<updated>2023-01-27T03:09:49Z</updated>
<author>
<name>Jessica Clarke</name>
<email>jrtc27@jrtc27.com</email>
</author>
<published>2023-01-26T15:40:03Z</published>
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<id>urn:sha1:c8ea836ee33eb778f48f780412e147386dac5301</id>
<content type='text'>
It seems BFD just does totally nonsensical things for SHN_ABS symbols
when producing position-independent outputs (both -pie and -shared)
for various historical reasons, and so SHN_ABS symbols are still
subject to relocation as far as BFD is concerned (except AArch64,
which fixes it in limited cases that don’t apply here...).

The above affects the _fw_rw_offset provided through fw_base.ldS
linker script which results in OpenSBI firmware failing to boot
when loaded at an address different from FW_TEXT_START.

Fixes: c10e3fe5f9a1 ("firmware: Add RW section offset in scratch")
Signed-off-by: Jessica Clarke &lt;jrtc27@jrtc27.com&gt;
Reported-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Tested-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Tested-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
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