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<title>opensbi.git/firmware/payloads, branch master</title>
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<updated>2026-03-10T05:17:23Z</updated>
<entry>
<title>lib: Use proper add opcode on RV32 with Zalrsc</title>
<updated>2026-03-10T05:17:23Z</updated>
<author>
<name>Marti Alonso</name>
<email>martialonso11@gmail.com</email>
</author>
<published>2026-03-01T20:54:21Z</published>
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<id>urn:sha1:b5348006e98077076a0b1a690c3a9f63c7151a4b</id>
<content type='text'>
The addw opcode is only defined in RV64, which produces 32-bit results.
On RV32, the default add opcode already produces 32-bit results.

Fixes: 995f226f3f33 ("lib: Emit lr and sc instructions based on -march flags")
Signed-off-by: Marti Alonso &lt;martialonso11@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: atomics: fix AMO test macros</title>
<updated>2025-12-28T15:14:03Z</updated>
<author>
<name>Vladimir Kondratiev</name>
<email>vladimir.kondratiev@mobileye.com</email>
</author>
<published>2025-12-28T07:33:21Z</published>
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<id>urn:sha1:f6fa62bd169e55f479b137da13ca83b27bb304a9</id>
<content type='text'>
The "RISC-V C API" [1] defines architecture extension test macros
says naming rule for the test macros is __riscv_&lt;ext_name&gt;, where
&lt;ext_name&gt; is all lower-case.

Three extensions dealing with atomics implementation are:
  "zaamo" consists of AMO instructions,
  "zalrsc" - LR/SC,
  "a" extension means both "zaamo" and "zalrsc"
Built-in test macros are __riscv_a, __riscv_zaamo and __riscv_zalrsc.
Alternative to the __riscv_a macro name, __riscv_atomic, is deprecated.

Use correct test macro __riscv_zaamo for the AMO variant of atomics.
It used to be __riscv_atomic that is both deprecated and incorrect
because it tests for the "a" extension; i.e. both "zaamo" and "zalrsc"
If ISA enables only zaamo but not zalrsc, code as it was would not compile.

Older toolchains may have neither __riscv_zaamo nor __riscv_zalrsc, so
query __riscv_atomic - it should be treated as both __riscv_zaamo and
__riscv_zalrsc, in all present cases __riscv_zaamo is more favorable
so take is as alternative for __riscv_zaamo

[1] https://github.com/riscv-non-isa/riscv-c-api-doc

Signed-off-by: Vladimir Kondratiev &lt;vladimir.kondratiev@mobileye.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20251228073321.1533844-1-vladimir.kondratiev@mobileye.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: payload: test: Add SBI shutdown call after test message</title>
<updated>2025-07-21T11:04:03Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2025-07-21T01:02:21Z</published>
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<id>urn:sha1:3876f8cd1e3c0c203a315bdc6e8ced176bb49e0a</id>
<content type='text'>
Previously, 'make run' would hang in WFI after printing the test message.
This commit adds an SBI ecall to ensure QEMU exits cleanly after the test
payload runs.

Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Link: https://lore.kernel.org/r/20250721010807.460788-1-wxjstz@126.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: Initial compiler built-in stack protector support</title>
<updated>2025-07-20T15:24:34Z</updated>
<author>
<name>Alvin Chang</name>
<email>alvinga@andestech.com</email>
</author>
<published>2025-07-03T15:19:57Z</published>
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<id>urn:sha1:edfbc1285dd9ac624665fe9fa5de26437d61c1eb</id>
<content type='text'>
Add __stack_chk_fail() and __stack_chk_guard variable which are used by
compiler built-in stack protector.

This patch just try to support stack-protector so the value of the stack
guard variable is simply fixed for now. It could be improved by
deriving from a random number generator, such as Zkr extension or any
platform-specific random number sources.

Introduce three configurations for the stack protector:
1. CONFIG_STACK_PROTECTOR to enable the stack protector feature by
   providing "-fstack-protector" compiler flag
2. CONFIG_STACK_PROTECTOR_STRONG to provide "-fstack-protector-strong"
3. CONFIG_STACK_PROTECTOR_ALL to provide "-fstack-protector-all"

Instead of fixing the compiler flag of stack-protector feature as
"-fstack-protector", we derive it from the introduced Kconfig
configurations. The compiler flag "stack-protector-cflags-y" is defined
as Makefile "immediately expanded variables" with ":=". Thus, the
stronger configuration of the stack protector can overwrite the
preceding one.

Signed-off-by: Alvin Chang &lt;alvinga@andestech.com&gt;
Reviewed-by: Yu-Chien Peter Lin &lt;peter.lin@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250703151957.2545958-3-alvinga@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: Emit lr and sc instructions based on -march flags</title>
<updated>2025-03-28T13:22:05Z</updated>
<author>
<name>Chao-ying Fu</name>
<email>icebergfu@gmail.com</email>
</author>
<published>2025-02-26T01:47:27Z</published>
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<id>urn:sha1:995f226f3f335864d2fca6254af32fa7ab0162e6</id>
<content type='text'>
When -march=rv64im_zalrsc_zicsr is used, provide atomic operations
and locks using lr and sc instructions only.

Signed-off-by: Chao-ying Fu &lt;cfu@mips.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250226014727.19710-1-cfu@mips.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: Bring back FW_TEXT_START as an optional parameter</title>
<updated>2024-05-23T05:20:23Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-05-15T04:25:50Z</published>
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<id>urn:sha1:96f0a2e3ea6dc8c337ad1b927d6bda8f5ac151be</id>
<content type='text'>
Bring back FW_TEXT_START as an optional parameter to allow users
explicitly specify compile time address for loading debug symbols.
When not specified, the FW_TEXT_START is assumed to be 0.

Fixes: d4d2582eef7a ("firmware: remove FW_TEXT_START")
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Clément Léger &lt;cleger@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>firmware: remove FW_TEXT_START</title>
<updated>2024-04-10T04:20:24Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2024-04-08T15:27:42Z</published>
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<id>urn:sha1:d4d2582eef7aac442076f955e4024403f8ff3d96</id>
<content type='text'>
Now opensbi can run at any address via dynamic relocation. We can
remove FW_TEXT_START.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Tested-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: fix section types</title>
<updated>2023-12-09T08:56:58Z</updated>
<author>
<name>Matt Waltz</name>
<email>matthewwaltzis@gmail.com</email>
</author>
<published>2023-12-05T15:13:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=06968103dcd99c2cf2dad97549ef3880ea00ccd2'/>
<id>urn:sha1:06968103dcd99c2cf2dad97549ef3880ea00ccd2</id>
<content type='text'>
These sections are only intended to hold data, and should not be executable.

Signed-off-by: Matt Waltz &lt;matthewwaltzis@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: payload: test: Change to SBI v2.0 DBCN ecalls</title>
<updated>2023-09-06T11:20:50Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-08-30T00:34:43Z</published>
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<id>urn:sha1:a9cffd65324caf5512e3ebb5b08d5b85efd0a23c</id>
<content type='text'>
As the the "Console Putchar" extension is already legacy and may
be removed in the furture. So replace it with the SBI v2.0 "DBCN"
extension.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: payloads: Optimize usage of "ALIGN"</title>
<updated>2022-11-22T05:50:11Z</updated>
<author>
<name>Leizheng Zhang</name>
<email>zhangleizheng@eswincomputing.com</email>
</author>
<published>2022-11-21T08:26:22Z</published>
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<id>urn:sha1:8e63716c1ce0ff5f8b5c3c2b515a3f1cda21f580</id>
<content type='text'>
Delete the redundant "ALIGN" and adjust the position of "ALIGN"

Signed-off-by: Leizheng Zhang &lt;zhangleizheng@eswincomputing.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng@tinylab.org&gt;
</content>
</entry>
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