opensbi.git/include/sbi/riscv_asm.h, branch master

lib: sbi: Move hart PMP functions to sbi_hart_pmp.c

2026-06-10T12:25:33Z

The sbi_hart_pmp.c looks like a good place for the hart PMP CSR access functions. Signed-off-by: Nicholas Piggin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260430045528.420437-9-npiggin@gmail.com Signed-off-by: Anup Patel

lib: sbi: Add hart_ prefix to PMP functions

2026-06-10T12:07:49Z

PMP functions that deal with hart PMP CSRs are given a sbi_hart_ prefix, to distinguish from RISC-V PMP encoding functions. The is_pmp_entry_mapped() function is changed a little more, to align with other PMP conventions, and made to return a bool to make it more obvious that it returns a bool and not an SBI_ return code. Signed-off-by: Nicholas Piggin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260430045528.420437-8-npiggin@gmail.com Signed-off-by: Anup Patel

include: riscv_asm: Optimize csr_xyz() macros to reduce stack usage

2025-12-27T05:51:27Z

When using debug builds, aka., DEBUG=1, csr_write_num() function can trigger stack overflow. This is caused by the large amount of macro expansion of csr_write(...), which, under debug builds, will generate massive amount of stack variables (tested with GCC 13.2.0). The issue is masked previously as we didn't have too many csr_write()'s before commit 55296fd27c0c, but now, it does overflow the default 4KB stack. The csr_read(relaxed) macros already use the "register" modifier to optimize stack usage (perhaps unknowingly?), so this patch just follows suit. Fixes: 55296fd27c0c ("lib: Allow custom CSRs in csr_read_num() and csr_write_num()") Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251216052528.18896-1-ganboing@gmail.com Signed-off-by: Anup Patel

lib: sbi: add 64 bit csr macros

2025-04-30T04:44:25Z

Most CSRs are XLEN bits wide, but some are 64 bit, so rv32 needs two accesses, plaguing the code with ifdefs. Add new helpers that split 64 bit operation into two operations on rv32. The helpers don't use "csr + 0x10", but append "H" at the end of the csr name to get a compile-time error when accessing a non 64 bit register. This has the downside that you have to use the name when accessing them. e.g. csr_read64(0x1234) or csr_read64(CSR_SATP) won't compile and the error messages you get for these bugs are not straightforward. Reviewed-by: Anup Patel Signed-off-by: Radim Krčmář Link: https://lore.kernel.org/r/20250429142549.3673976-3-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel

include: sbi: Optimize reads of mhartid and mscratch

2024-10-28T05:21:37Z

csr_read() is marked as volatile and clobbering memory, which is generally the safe thing to do. However, these two CSRs do not have any side effects, and the values returned do not change between calls. The compiler can generate better code if we allow it to reorder calls to these functions and cache the return value. Introduce csr_read_relaxed() for this use case. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: sbi: Add functions to manipulate PMP entries

2023-07-13T06:40:39Z

- Add a function to disable a given PMP entry. - Add a function to check if a given entry is disabled. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel

lib: utils: reset: Add T-HEAD sample platform reset driver

2021-04-22T09:43:53Z

This driver is for T-HEAD test chip, fpga. It could work with all T-HEAD riscv processors: C9xx series. example1: (Using io-regs for reset) reset: reset-sample { compatible = "thead,reset-sample"; plic-delegate = <0xff 0xd81ffffc>; entry-reg = <0xff 0xff019050>; entry-cnt = <4>; control-reg = <0xff 0xff015004>; control-val = <0x1c>; csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; }; example2: (Using csr-regs for reset) reset: reset-sample { compatible = "thead,reset-sample"; plic-delegate = <0xff 0xd81ffffc>; using-csr-reset; csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x3b0 0x3b1 0x3b2 0x3b3 0x3b4 0x3b5 0x3b6 0x3b7 0x3a0>; }; example3: (Only delegate plic enable to S-mode) reset: reset-sample { compatible = "thead,reset-sample"; plic-delegate = <0xff 0xd81ffffc>; }; After this patch, all T-HEAD c9xx would use platform/generic with fw_dynamic as default: CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make The platform/thead will be deprecated. Signed-off-by: Guo Ren Reviewed-by: Anup Patel

include: headers: Replace ASSEMBLY with ASSEMBLER

2021-03-22T10:32:48Z

GCC has already a predefined macro __ASSEMBLER__ therefore, it can be used without the need to define a new flag with -D__ASSEMBLY__. This is useful when adding the library to projects having a build system such one can build without the need to make changes. THe build system does not use the Makefile in the sources tree. Signed-off-by: Marouene Boubakri Signed-off-by: Anup Patel

lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API

2020-09-16T03:35:25Z

We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Improve misa_string() implementation

2020-05-07T03:38:26Z

The RISC-V ISA string does not follow alphabetical order. Instead, we have a RISC-V specific ordering of extensions in the RISC-V ISA string. This patch improves misa_string() implementation to return a valid RISC-V ISA string. Signed-off-by: Anup Patel Reviewed-by: Atish Patra