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<title>opensbi.git/include/sbi/riscv_asm.h, branch v0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/include/sbi/riscv_asm.h?h=v0.2</id>
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<updated>2019-02-05T13:23:09Z</updated>
<entry>
<title>riscv_asm.h: Use CSR_&lt;FOO&gt; instead of &lt;foo&gt; for csr_read()</title>
<updated>2019-02-05T13:23:09Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2019-02-04T02:49:20Z</published>
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<id>urn:sha1:c0addfe751e51376a73df71336ce11826e68c939</id>
<content type='text'>
Some toolchains might not have all the CSRs available (as seen with
GCC 7.2). So, instead use the defined CSR_ values.

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>all: Update copyright header in all files</title>
<updated>2019-01-24T08:37:47Z</updated>
<author>
<name>Anup patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2019-01-24T06:11:10Z</published>
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<id>urn:sha1:20990ee0abaf286917b6e2aae992d4183ff695f6</id>
<content type='text'>
This patch updates copyright header in all files as follows:
1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line
2. Change copyright year to 2019 for Western Digital

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Add atomic bit set/clear operations.</title>
<updated>2019-01-22T04:33:49Z</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2019-01-21T07:23:28Z</published>
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<id>urn:sha1:312b6bf32f51e530dd22746fe2a36d6459e29588</id>
<content type='text'>
Add addtional functionlities for set/clear bits
atomically.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: Move RISCV_TRAP_REGS_xyz defines to sbi_trap.h</title>
<updated>2019-01-02T04:27:12Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2018-12-31T07:07:28Z</published>
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<id>urn:sha1:dc7be34d523f93d2834f4aff49d640cdec16a509</id>
<content type='text'>
The struct sbi_trap_regs related defines RISCV_TRAP_REGS_xyz should
be in sbi_trap.h so that we can keep these defines in-sync with changes
in struct sbi_trap_regs.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: Move RISCV_PLATFORM_xyz defines to sbi_platform.h</title>
<updated>2019-01-02T04:27:12Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2018-12-31T06:00:55Z</published>
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<id>urn:sha1:5ed3cf37073125a38ac839ad11de687f20286b33</id>
<content type='text'>
The struct sbi_platform related defines RISCV_PLATFORM_xyz should
be in sbi_platform.h so that we can keep these defines in-sync
with changes in struct sbi_platform.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: Move RISCV_SCRATCH_xyz defines to sbi_scratch.h</title>
<updated>2019-01-02T04:27:12Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2018-12-31T05:49:20Z</published>
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<id>urn:sha1:e0d6914b3c40c1609ccf196fa448ea6880ff23d5</id>
<content type='text'>
The struct sbi_scratch related defines RISCV_SCRATCH_xyz should
be in sbi_scratch.h so that we can keep these defines in-sync
with changes in struct sbi_scratch.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: Replace #csr with __ASM_STR(csr) in csr_xyz() macros</title>
<updated>2019-01-02T04:27:12Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2018-12-31T04:59:49Z</published>
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<id>urn:sha1:24bfa687fc85f0c8b0b2ed60151e44e9b7c43d3b</id>
<content type='text'>
We replace #csr with __ASM_STR(csr) in all csr_xyz() macros
so that we can pass CSR number instead of CSR name when GCC
is not aware of CSR name.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: Remove redundant csr_read_n() and csr_write_n()</title>
<updated>2019-01-02T04:27:12Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2018-12-31T04:55:42Z</published>
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<id>urn:sha1:81e8950abeb649a0842726fdfc1aa4e60b1008f5</id>
<content type='text'>
The patch removes redundant csr_read_n() and csr_write_n()
because same thing can be achieved by using __ASM_STR()
macro in csr_read() and csr_write() macros.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>firmware: Don't depend on PLAT_HART_COUNT and PLAT_HART_STACK_SIZE</title>
<updated>2018-12-22T15:19:52Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2018-12-22T07:10:54Z</published>
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<id>urn:sha1:58ca525a7d35b2d4cd7045fd343fb6d85567f01d</id>
<content type='text'>
The hart_count and hart_stack_size information is already available
in "struct sbi_platform" so we use that instead of depending on
PLAT_HART_COUNT and PLAT_HART_STACK_SIZE.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>Initial commit.</title>
<updated>2018-12-11T13:54:06Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2018-12-11T13:54:06Z</published>
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<id>urn:sha1:9e8ff05cb61f157fb0bcb6b0071d7b6dc0763faa</id>
<content type='text'>
Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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