opensbi.git/include/sbi/riscv_asm.h, branch v1.2

lib: utils: reset: Add T-HEAD sample platform reset driver

2021-04-22T09:43:53Z

This driver is for T-HEAD test chip, fpga. It could work with all T-HEAD riscv processors: C9xx series. example1: (Using io-regs for reset) reset: reset-sample { compatible = "thead,reset-sample"; plic-delegate = <0xff 0xd81ffffc>; entry-reg = <0xff 0xff019050>; entry-cnt = <4>; control-reg = <0xff 0xff015004>; control-val = <0x1c>; csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; }; example2: (Using csr-regs for reset) reset: reset-sample { compatible = "thead,reset-sample"; plic-delegate = <0xff 0xd81ffffc>; using-csr-reset; csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x3b0 0x3b1 0x3b2 0x3b3 0x3b4 0x3b5 0x3b6 0x3b7 0x3a0>; }; example3: (Only delegate plic enable to S-mode) reset: reset-sample { compatible = "thead,reset-sample"; plic-delegate = <0xff 0xd81ffffc>; }; After this patch, all T-HEAD c9xx would use platform/generic with fw_dynamic as default: CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make The platform/thead will be deprecated. Signed-off-by: Guo Ren Reviewed-by: Anup Patel

include: headers: Replace ASSEMBLY with ASSEMBLER

2021-03-22T10:32:48Z

GCC has already a predefined macro __ASSEMBLER__ therefore, it can be used without the need to define a new flag with -D__ASSEMBLY__. This is useful when adding the library to projects having a build system such one can build without the need to make changes. THe build system does not use the Makefile in the sources tree. Signed-off-by: Marouene Boubakri Signed-off-by: Anup Patel

lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API

2020-09-16T03:35:25Z

We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Improve misa_string() implementation

2020-05-07T03:38:26Z

The RISC-V ISA string does not follow alphabetical order. Instead, we have a RISC-V specific ordering of extensions in the RISC-V ISA string. This patch improves misa_string() implementation to return a valid RISC-V ISA string. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Update pmp_get() to return decoded size directly

2020-03-18T03:28:26Z

Currently pmp_get() returns the log2 length of the PMP memory region size. The caller has to calculate the size based on that and the same codes are duplicated. Update this function to return decoded size directly. Signed-off-by: Bin Meng Reviewed-by: Atish Patra

include: Make sbi_current_hartid() as macro in riscv_asm.h

2020-03-13T06:52:02Z

The sbi_current_hartid() being a regular function is quite expensive because for callers it is a function call instead of a direct CSR read. This patch converts sbi_current_hartid() into a macro in riscv_asm.h. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Fix coding style issues

2020-03-10T04:57:28Z

This fixes various coding style issues found in the SBI codes. No functional changes. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

include: Move bits related defines and macros to sbi_bitops.h

2020-03-08T05:36:18Z

The right location for all bits related defines and macros is sbi_bitops.h hence this patch. With this patch, the sbi_bits.h is redundant so we remove it. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Add error detection for misa_extension

2019-11-27T06:40:33Z

Add assertions for misa_extension to prevent incoming illegal characters. Signed-off-by: Xiang Wang Reviewed-by: Anup Patel

lib: Fix CPU capabilities detection function

2019-11-26T10:36:29Z

On some platforms, misa may not be implemented. On such a platform, reading misa will get 0. At this time, platform is required to implement a non-standard function to detect the CPU's capabilities. Therefore, this modification add interfaces for non-standard function. The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length. Signed-off-by: Xiang Wang Signed-off-by: Anup Patel