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<title>opensbi.git/include/sbi/riscv_dbtr.h, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/include/sbi/riscv_dbtr.h?h=master</id>
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<updated>2025-08-28T05:06:52Z</updated>
<entry>
<title>dbtr: Add support for icount trigger type</title>
<updated>2025-08-28T05:06:52Z</updated>
<author>
<name>Jesse Taube</name>
<email>jesse@rivosinc.com</email>
</author>
<published>2025-07-24T18:31:20Z</published>
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<id>urn:sha1:4b687e36695edef8233bfca758b8d05a74b9a6de</id>
<content type='text'>
The linux kernel needs icount to implement hardware breakpoints.

Signed-off-by: Jesse Taube &lt;jesse@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250724183120.1822667-1-jesse@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: sbi: Introduce debug trigger register encodings</title>
<updated>2024-01-10T04:13:34Z</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2024-01-09T17:00:15Z</published>
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<id>urn:sha1:24997697aed9856f2a7e6ea73802e4939010660e</id>
<content type='text'>
This patch introduces Mcontrol and M6 control register
encodings along with macros to manipulate them.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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