opensbi.git/include/sbi/riscv_encoding.h, branch v0.8

lib: Add RISC-V hypervisor v0.6.1 support

2020-06-08T10:11:23Z

To support RISC-V hypervisor v0.6.1, we: 1. Don't need to explicitly forward WFI traps from VS/VU-mode 2. Have to delegate virtual instruction trap to HS-mode 3. Have to update trap redirection for changes in HSTATUS CSR Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementation

2020-05-07T03:25:38Z

The HFENCE VVMA instructions flushes TLB based on the VMID present in HGATP CSR. To handle this, we get the current VMID for SBI HFENCE VVMA call and we use this current VMID to do remote TLB HFENCE VVMA on desired set of HARTs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

include: sbi: Remove redundant page table related defines

2020-05-07T03:25:02Z

We don't have page table programming in OpenSBI so let's remove redundant page table related defines from riscv_encoding.h. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Support vector extension

2020-04-17T04:00:17Z

Enable vector context in mstatus by updating the corresponding bits in mstatus if vector extension is supported by the hart. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Reviewed-by: Anup Patel

lib: Extend trap redirection for hypervisor v0.5 spec

2019-12-16T09:18:26Z

The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel

include: Add guest external interrupt related defines

2019-12-16T09:18:12Z

With RISC-V H-extension v0.5 draft, we have special support for guest external interrupts so this patch adds related defines which were missed-out previously. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis

include: Use _UL() and _ULL() for defines in riscv_encoding.h

2019-11-06T05:07:24Z

The riscv_encoding.h is shared with assembly sources so we use _UL() and _ULL() for register fields related defines. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

include: Sync-up encoding with priv v1.12-draft and hypervisor v0.5-draft

2019-11-06T05:05:41Z

This patch sync-up encoding header with the latest privilege specifications draft v1.12 and hypervisor specifications draft v0.5. The MSTATUS.MTL and HSTATUS.STL bits are not present anymore and will be removed by another patch series for hypervisor v0.5-draft. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSR

2019-09-30T10:06:14Z

For platforms not having TIME CSR, we trap-n-emulate TIME CSR read/write in OpenSBI. Same rationale applies to HTIMEDELTA CSR as well so we trap-n-emulate HTIMEDELTA CSR for platforms not having TIME CSR. Signed-off-by: Anup Patel

lib: Redirect WFI trapped from VS/VU mode to HS-mode

2019-09-30T10:02:00Z

The WFI will trap as illegal instruction trap when executed in VS/VU mode so we just forward/redirect it to HS-mode so that hypervisor can deal with it appropriately. Signed-off-by: Anup Patel