opensbi.git/include/sbi/riscv_encoding.h, branch v0.9

include: Rename ECALL defines to match latest RISC-V spec

2020-09-09T04:02:02Z

We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that it matches latest RISC-V privilege spec. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

include: sbi: Few cosmetic changes in riscv_encoding.h

2020-09-01T04:58:33Z

This patch does following cosmentic changes to riscv_encoding.h: 1. Re-organize CSR defines to match CSR listing in latest RISC-V privilege spec 2. Rename CSR_HCOUNTERNEN to CSR_HCOUNTEREN Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Improve PMP CSR detection and progamming

2020-09-01T04:58:28Z

As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Add RISC-V hypervisor v0.6.1 support

2020-06-08T10:11:23Z

To support RISC-V hypervisor v0.6.1, we: 1. Don't need to explicitly forward WFI traps from VS/VU-mode 2. Have to delegate virtual instruction trap to HS-mode 3. Have to update trap redirection for changes in HSTATUS CSR Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementation

2020-05-07T03:25:38Z

The HFENCE VVMA instructions flushes TLB based on the VMID present in HGATP CSR. To handle this, we get the current VMID for SBI HFENCE VVMA call and we use this current VMID to do remote TLB HFENCE VVMA on desired set of HARTs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

include: sbi: Remove redundant page table related defines

2020-05-07T03:25:02Z

We don't have page table programming in OpenSBI so let's remove redundant page table related defines from riscv_encoding.h. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Support vector extension

2020-04-17T04:00:17Z

Enable vector context in mstatus by updating the corresponding bits in mstatus if vector extension is supported by the hart. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Reviewed-by: Anup Patel

lib: Extend trap redirection for hypervisor v0.5 spec

2019-12-16T09:18:26Z

The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel

include: Add guest external interrupt related defines

2019-12-16T09:18:12Z

With RISC-V H-extension v0.5 draft, we have special support for guest external interrupts so this patch adds related defines which were missed-out previously. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis

include: Use _UL() and _ULL() for defines in riscv_encoding.h

2019-11-06T05:07:24Z

The riscv_encoding.h is shared with assembly sources so we use _UL() and _ULL() for register fields related defines. Signed-off-by: Anup Patel Reviewed-by: Atish Patra