opensbi.git/include/sbi/riscv_encoding.h, branch v1.0

lib: sbi: Support sscofpmf extension in OpenSBI

2021-11-11T12:16:57Z

This patch adds sscofpmf extension in pmu module which includes following things. 1. Enable overflow irq when starting a counter. 2. Setting the correct event filters passed from supervisor. 3. Delegating the overflow interrupt to the supervisor. 4. Add RV32 support for sscofpmf. Reviewed-by: Anup Patel Reviewed-by: Bin Meng Signed-off-by: Atish Patra

lib: sbi: Delegate PMU counter overflow interrupt to S mode

2021-11-11T12:15:12Z

OpenSBI doesn't handle PMU counters for now. Delegate the overflow counter to S-mode always. Reviewed-by: Bin Meng Reviewed-by: Anup Patel Signed-off-by: Atish Patra

riscv: Add new CSRs introduced by Sscofpmf[1] extension

2021-11-11T12:07:34Z

[1] https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view Reviewed-by: Xiang W Reviewed-by: Bin Meng Reviewed-by: Anup Patel Signed-off-by: Atish Patra

include: Rename ECALL defines to match latest RISC-V spec

2020-09-09T04:02:02Z

We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that it matches latest RISC-V privilege spec. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

include: sbi: Few cosmetic changes in riscv_encoding.h

2020-09-01T04:58:33Z

This patch does following cosmentic changes to riscv_encoding.h: 1. Re-organize CSR defines to match CSR listing in latest RISC-V privilege spec 2. Rename CSR_HCOUNTERNEN to CSR_HCOUNTEREN Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Improve PMP CSR detection and progamming

2020-09-01T04:58:28Z

As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Add RISC-V hypervisor v0.6.1 support

2020-06-08T10:11:23Z

To support RISC-V hypervisor v0.6.1, we: 1. Don't need to explicitly forward WFI traps from VS/VU-mode 2. Have to delegate virtual instruction trap to HS-mode 3. Have to update trap redirection for changes in HSTATUS CSR Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementation

2020-05-07T03:25:38Z

The HFENCE VVMA instructions flushes TLB based on the VMID present in HGATP CSR. To handle this, we get the current VMID for SBI HFENCE VVMA call and we use this current VMID to do remote TLB HFENCE VVMA on desired set of HARTs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

include: sbi: Remove redundant page table related defines

2020-05-07T03:25:02Z

We don't have page table programming in OpenSBI so let's remove redundant page table related defines from riscv_encoding.h. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Support vector extension

2020-04-17T04:00:17Z

Enable vector context in mstatus by updating the corresponding bits in mstatus if vector extension is supported by the hart. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Reviewed-by: Anup Patel