opensbi.git/include/sbi/riscv_encoding.h, branch v1.2

include: Remove sideleg and sedeleg

2022-09-01T10:07:22Z

sideleg and sedeleg csrs are not part of riscv isa spec anymore, these csrs were part of N extension which is removed from the riscv isa specification. These commits removed all traces of these csrs from riscv spec (https://github.com/riscv/riscv-isa-manual) - commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)") commit b6cade07034d ("Remove N extension chapter for now") Signed-off-by: Rahul Pathak Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

include: Add mstatus[h].GVA encodings

2022-08-22T03:19:29Z

The machine mode GVA field is in mstatus for RV64 and mstatush for RV32, and is available if the hypervisor extension is available. If an exception occurs, we may need to redirect the trap to HS-mode, in which case, hstatus.GVA should be set to same as the machine mode GVA bit. Add MSTATUS_GVA for RV64, MSTATUSH_GVA for RV32, and their SHIFT encodings. The SHIFT index is helpful in assembly code, since field extraction can be implemented in only one register. In pseudocode: - For RV32: gva = (mstatus >> MSTATUS_GVA_SHIFT) & 1; - For RV64: gva = (mstatush >> MSTATUSH_GVA_SHIFT) & 1; Signed-off-by: Vivian Wang Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bits

2022-06-21T03:14:45Z

Based on architecture review committee feedback, the [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are removed in the latest AIA draft v0.3.0 specification. (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31) These CSRs were mostly for software convenience and software can always use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt file bits. We update the IMSIC programming as-per above to match the latest AIA draft specification. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

include: sbi: Add mtinst/htinst psuedoinstructions

2022-06-21T03:01:04Z

Add psuedoinstruction encodings written to mtinst/htinst for faults caused by implicit memory access for VS-stage address translation Signed-off-by: dramforever Reviewed-by: Anup Patel

lib: sbi_illegal_insn: Add emulation for fence.tso

2022-06-01T11:50:20Z

While OpenC906 appears to properly decode `fence.tso` as a fence instruction[1], the version of the C906 taped out in the Allwinner D1 does not, and raises illegal instruction. Handle this errata by emulating `fence.tso` as `fence rw, rw`. [1]: https://github.com/T-head-Semi/openc906/blob/30827e7f/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_decd.v#L2097 Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: sbi: Implement Sstc extension

2022-04-28T06:15:21Z

Recently, Sstc extension was ratified. It defines stimecmp which allows the supervisor mode to directly update the timecmp value without the need of the SBI call. The hardware also can inject the S-mode timer interrupt direclty to the supervisor without going through the M-mode. To maintain backward compatibility with the older software, SBI call now uses stimecmp directly if the hardware supports. Implement the Sstc extension. Signed-off-by: Atish Patra Reviewed-by: Anup Patel

include: correct the definition of MSTATUS_VS

2022-04-17T09:00:19Z

Accordind to the RISC-V privileged specification, the VS filed is mstatus[10:9] instead of mstatus[24:23]. Modify the MSTATUS_VS to the correct value. Reported-by: I-Cheng Cheng Signed-off-by: Vincent Chen Reviewed-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Add Smstateen extension defines

2022-04-11T03:04:02Z

Smstateen extension provides a mechanism to plug potential covert channels which are opened by extensions that add to processor state that may not get context-switched. Signed-off-by: Mayuresh Chitale Reviewed-by: Xiang W Reviewed-by: Anup Patel

include: Add defines for [m|h|s]envcfg CSRs

2022-04-05T03:20:17Z

The latest RISC-V privileged specification introduces xenvcfg CSRs to enable/disable certain features/extensions for lower privilege modes. This patch adds defines for these new [m|h|s]envcfg CSRs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Xiang W

include: sbi: Add AIA related CSR defines

2022-02-15T15:02:07Z

The RISC-V AIA specification improves handling of per-HART local interrupts in a backward compatible manner. This patch adds defines for the new RISC-V AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Atish Patra