opensbi.git/include/sbi/riscv_encoding.h, branch v1.4

lib: sbi: Refactor the code for enable extensions in menvfg CSR

2023-12-19T08:24:33Z

Use 1 variable to store the value of menvcfg. Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel

include: sbi: macros for mseccfg.sseed and .useed

2023-11-17T06:33:59Z

Define macros to access the sseed and the useed bit in the machine security configuration register (mseccfg). Signed-off-by: Heinrich Schuchardt Reviewed-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Add support for mconfigptr

2023-10-06T12:28:42Z

RISC-V privileged specification v1.12 introduced the mconfigptr CSR which will hold the physical address of a configuration data structure. Signed-off-by: Yangjie Zhang Reviewed-by: Anup Patel

lib: sbi: Add support for smcntrpmf

2023-08-18T09:20:38Z

This adds the support for ISA extension smcntrpmf. When some inhibit flags are set by a lower privilege mode for new CSRs added by smcntrpmf, OpenSBI sets the appropriate values correspondingly. Signed-off-by: Kaiwen Xue Signed-off-by: Kaiwen Xue Reviewed-by: Anup Patel Reviewed-by: Atish Patra

include: sbi: fix CSR define of mseccfg

2023-07-31T06:21:49Z

Because the CSR names in the spec are mseccfg and mseccfgh. Remove CSR_MSECCFG_LOWER and CSR_MSECCFG_UPPER and directly define CSR_MSECCFG and CSR_MSECCFGH. Signed-off-by: Xiang W Reviewed-by: Anup Patel

include: sbi: Add macro definitions for mseccfg CSR

2023-07-13T06:39:34Z

- Add macros for Machine Security Configuration (mseccfg) CSR - Add macros to access/manipulate bits in msecfg CSR Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel

lib: sbi_hart: Enable hcontext and scontext

2023-02-27T05:52:11Z

According to the description in "riscv-state-enable[0]", to access h/scontext in S-Mode, we need to enable the 57th bit. If it is not enabled, an "illegal instruction" error will occur. Link: https://github.com/riscv/riscv-state-enable/blob/a28bfae443f350d5b4c42874f428367d5b322ffe/content.adoc [0] Signed-off-by: Nylon Chen Reviewed-by: Zong Li Reviewed-by: Anup Patel

include: Remove sideleg and sedeleg

2022-09-01T10:07:22Z

sideleg and sedeleg csrs are not part of riscv isa spec anymore, these csrs were part of N extension which is removed from the riscv isa specification. These commits removed all traces of these csrs from riscv spec (https://github.com/riscv/riscv-isa-manual) - commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)") commit b6cade07034d ("Remove N extension chapter for now") Signed-off-by: Rahul Pathak Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

include: Add mstatus[h].GVA encodings

2022-08-22T03:19:29Z

The machine mode GVA field is in mstatus for RV64 and mstatush for RV32, and is available if the hypervisor extension is available. If an exception occurs, we may need to redirect the trap to HS-mode, in which case, hstatus.GVA should be set to same as the machine mode GVA bit. Add MSTATUS_GVA for RV64, MSTATUSH_GVA for RV32, and their SHIFT encodings. The SHIFT index is helpful in assembly code, since field extraction can be implemented in only one register. In pseudocode: - For RV32: gva = (mstatus >> MSTATUS_GVA_SHIFT) & 1; - For RV64: gva = (mstatush >> MSTATUSH_GVA_SHIFT) & 1; Signed-off-by: Vivian Wang Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bits

2022-06-21T03:14:45Z

Based on architecture review committee feedback, the [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are removed in the latest AIA draft v0.3.0 specification. (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31) These CSRs were mostly for software convenience and software can always use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt file bits. We update the IMSIC programming as-per above to match the latest AIA draft specification. Signed-off-by: Anup Patel Reviewed-by: Atish Patra