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<title>opensbi.git/include/sbi/riscv_encoding.h, branch v1.5</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/include/sbi/riscv_encoding.h?h=v1.5</id>
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<updated>2024-06-18T11:11:32Z</updated>
<entry>
<title>lib: sbi: Add support for Svade and Svadu extensions</title>
<updated>2024-06-18T11:11:32Z</updated>
<author>
<name>Yong-Xuan Wang</name>
<email>yongxuan.wang@sifive.com</email>
</author>
<published>2024-06-05T12:11:09Z</published>
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<id>urn:sha1:53844c98d082cbba29a6e568196add6de95e858f</id>
<content type='text'>
Add support for Svade and Svadu extensions. When both are present in the
device tree, the M-mode firmware should select the Svade extension
to comply with the RVA23 profile, which mandates Svade and lists Svadu as
an optional extension.

Signed-off-by: Yong-Xuan Wang &lt;yongxuan.wang@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Remove regs parameter from trap irq handling functions</title>
<updated>2024-03-19T06:01:35Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-03-11T12:30:50Z</published>
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<id>urn:sha1:43d346c0c1d3817d863741c3c523ab6e0c87cc6f</id>
<content type='text'>
The trap irq handling functions no longer require regs parameter
so remove it.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Tested-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi_misaligned_ldst: Add handling of C.LHU/C.LH and C.SH</title>
<updated>2024-03-05T04:01:52Z</updated>
<author>
<name>Nylon Chen</name>
<email>nylon.chen@sifive.com</email>
</author>
<published>2024-02-26T05:56:44Z</published>
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<id>urn:sha1:748bef1f9d6c4da16d07a8152566f3f921b8702c</id>
<content type='text'>
Added exception handling for compressed instructions C.LHU, C.LH, and
C.SH from the zcb extension to the sbi_misaligned_ldst library.

Signed-off-by: Nylon Chen &lt;nylon.chen@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add support for smcsrind and smcdeleg</title>
<updated>2024-03-04T04:50:41Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-02-17T00:06:08Z</published>
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<id>urn:sha1:6bb6b61c27eb07da375213a7a1bb0f8e3fad663a</id>
<content type='text'>
Smcsrind allows generic indirect CSR access mechanism while
Smcdeleg allows delegating hpmcounters in Supervisor mode.

Enable both extensions and set the appropriate bits in mstateen
and menvcfg.

Co-developed-by: Kaiwen Xue &lt;kaiwenxue1@gmail.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: sbi: Add TINFO debug trigger CSR</title>
<updated>2024-01-10T04:13:33Z</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2024-01-09T17:00:14Z</published>
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<id>urn:sha1:20ca19ab0323bb3b162a620008d192e2a56302a2</id>
<content type='text'>
Add the missing TINFO debug trigger CSR.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Refactor the code for enable extensions in menvfg CSR</title>
<updated>2023-12-19T08:24:33Z</updated>
<author>
<name>Yong-Xuan Wang</name>
<email>yongxuan.wang@sifive.com</email>
</author>
<published>2023-12-12T08:58:33Z</published>
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<id>urn:sha1:056fe6f85dc6b68783f56cb6ea7394e857ab8cc3</id>
<content type='text'>
Use 1 variable to store the value of menvcfg.

Signed-off-by: Yong-Xuan Wang &lt;yongxuan.wang@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: sbi: macros for mseccfg.sseed and .useed</title>
<updated>2023-11-17T06:33:59Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-10-28T22:49:57Z</published>
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<id>urn:sha1:280f7ae62724b184fdd61347e6f905bc39dec64b</id>
<content type='text'>
Define macros to access the sseed and the useed bit in the machine
security configuration register (mseccfg).

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add support for mconfigptr</title>
<updated>2023-10-06T12:28:42Z</updated>
<author>
<name>Yangjie Zhang</name>
<email>jay1273062855@outlook.com</email>
</author>
<published>2023-09-28T08:27:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=3632f2b5c43e2a01bbfdcf4864d358845dcf281e'/>
<id>urn:sha1:3632f2b5c43e2a01bbfdcf4864d358845dcf281e</id>
<content type='text'>
RISC-V privileged specification v1.12 introduced the mconfigptr CSR
which will hold the physical address of a configuration data
structure.

Signed-off-by: Yangjie Zhang &lt;jay1273062855@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add support for smcntrpmf</title>
<updated>2023-08-18T09:20:38Z</updated>
<author>
<name>Kaiwen Xue</name>
<email>kaiwenx@rivosinc.com</email>
</author>
<published>2023-07-20T21:07:02Z</published>
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<id>urn:sha1:c104c60912a4ed26093f00a9675ad0286e8dcd29</id>
<content type='text'>
This adds the support for ISA extension smcntrpmf. When some inhibit flags
are set by a lower privilege mode for new CSRs added by smcntrpmf, OpenSBI
sets the appropriate values correspondingly.

Signed-off-by: Kaiwen Xue &lt;kaiwenx@andrew.cmu.edu&gt;
Signed-off-by: Kaiwen Xue &lt;kaiwenx@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>include: sbi: fix CSR define of mseccfg</title>
<updated>2023-07-31T06:21:49Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2023-07-14T10:08:34Z</published>
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<id>urn:sha1:5e20d25f19472e98e53f24fe9183ded6de04bce9</id>
<content type='text'>
Because the CSR names in the spec are mseccfg and mseccfgh. Remove
CSR_MSECCFG_LOWER and CSR_MSECCFG_UPPER and directly define
CSR_MSECCFG and CSR_MSECCFGH.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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