opensbi.git/include/sbi/riscv_encoding.h, branch v1.5.1

include: Adjust Sscofpmf mhpmevent mask for upper 8 bits

2024-08-02T03:23:17Z

Currently, OpenSBI reserves the upper 16 bits in mhpmevent for the Sscofpmf extension. However, according to the Sscofpmf extension specification[1], it only defines the upper 8 bits in mhpmevent for privilege mode inhibit and counter overflow disable. Other bits are defined by the platform for event selection. Since vendors might define raw event encoding exceeding 48 bits in mhpmevent, we should adjust the MHPMEVENT_SSCOF_MASK to support it. Link: https://github.com/riscvarchive/riscv-count-overflow [1] Signed-off-by: Eric Lin Reviewed-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Add support for Svade and Svadu extensions

2024-06-18T11:11:32Z

Add support for Svade and Svadu extensions. When both are present in the device tree, the M-mode firmware should select the Svade extension to comply with the RVA23 profile, which mandates Svade and lists Svadu as an optional extension. Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel

lib: sbi: Remove regs parameter from trap irq handling functions

2024-03-19T06:01:35Z

The trap irq handling functions no longer require regs parameter so remove it. Signed-off-by: Anup Patel Reviewed-by: Samuel Holland Tested-by: Samuel Holland

lib: sbi_misaligned_ldst: Add handling of C.LHU/C.LH and C.SH

2024-03-05T04:01:52Z

Added exception handling for compressed instructions C.LHU, C.LH, and C.SH from the zcb extension to the sbi_misaligned_ldst library. Signed-off-by: Nylon Chen Reviewed-by: Anup Patel

lib: sbi: Add support for smcsrind and smcdeleg

2024-03-04T04:50:41Z

Smcsrind allows generic indirect CSR access mechanism while Smcdeleg allows delegating hpmcounters in Supervisor mode. Enable both extensions and set the appropriate bits in mstateen and menvcfg. Co-developed-by: Kaiwen Xue Signed-off-by: Atish Patra Reviewed-by: Anup Patel

include: sbi: Add TINFO debug trigger CSR

2024-01-10T04:13:33Z

Add the missing TINFO debug trigger CSR. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel

lib: sbi: Refactor the code for enable extensions in menvfg CSR

2023-12-19T08:24:33Z

Use 1 variable to store the value of menvcfg. Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel

include: sbi: macros for mseccfg.sseed and .useed

2023-11-17T06:33:59Z

Define macros to access the sseed and the useed bit in the machine security configuration register (mseccfg). Signed-off-by: Heinrich Schuchardt Reviewed-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Add support for mconfigptr

2023-10-06T12:28:42Z

RISC-V privileged specification v1.12 introduced the mconfigptr CSR which will hold the physical address of a configuration data structure. Signed-off-by: Yangjie Zhang Reviewed-by: Anup Patel

lib: sbi: Add support for smcntrpmf

2023-08-18T09:20:38Z

This adds the support for ISA extension smcntrpmf. When some inhibit flags are set by a lower privilege mode for new CSRs added by smcntrpmf, OpenSBI sets the appropriate values correspondingly. Signed-off-by: Kaiwen Xue Signed-off-by: Kaiwen Xue Reviewed-by: Anup Patel Reviewed-by: Atish Patra