opensbi.git/include/sbi/riscv_encoding.h, branch v1.6

lib: sbi_misaligned_ldst: Add handling of vector load/store

2024-12-06T12:13:06Z

Add misaligned load/store handling for the vector extension to the sbi_misaligned_ldst library. This implementation is inspired from the misaligned_vec_ldst implementation in the riscv-pk project. Co-developed-by: Zong Li Signed-off-by: Zong Li Signed-off-by: Nylon Chen Reviewed-by: Andy Chiu Reviewed-by: Anup Patel

lib: sbi: add Smdbltrp ISA extension support

2024-10-25T18:30:12Z

Add support for the Smdbltrp[1] ISA extension. First thing to do is clearing MDT on entry after setting the first MTVEC (since MDT is reset to 1). Additionally, during trap handling, clear MDT once all critical CSRs have been saved and in return path, restore MSTATUS/H before restoring MEPC to avoid taking another trap which would clobber it. Link: https://github.com/riscv/riscv-double-trap/releases/download/v0.56/riscv-double-trap.pdf [1] Signed-off-by: Clément Léger Reviewed-by: Samuel Holland

lib: sbi: implement firmware feature SBI_FWFT_DOUBLE_TRAP

2024-10-25T18:29:27Z

Add support for double trap firmware feature. Link: https://lists.riscv.org/g/tech-prs/message/985 [1] Signed-off-by: Clément Léger Reviewed-by: Samuel Holland

lib: sbi: fwft: factorize menvcfg read/write

2024-10-25T18:28:58Z

MENVCFG access will be used as well for double trap, landing pad and shadow stack fwft support. Factorize that in a common function. Signed-off-by: Clément Léger Reviewed-by: Samuel Holland

lib: sbi: add Ssdbltrp ISA extension support

2024-10-25T18:28:00Z

Add Ssdbltrp trap handler support for S-mode double trap handling. If the trap is received while in VS-mode, then the trap is redirected to S-mode. If caught while in HS-mode, then an error is returned to the top trap handler which will panic. Signed-off-by: Clément Léger Reviewed-by: Samuel Holland

include: adding support for Zicfilp / Zicfiss encodings

2024-09-23T13:25:07Z

Zicfilp / Zicfiss extension (see link) introduces b2 (LPE) in menvcfg CSR to enable landing pads and b3 (SSE) in menvcfg CSR to enable shadow stack and landing pad for privilege less than M. Additionally extension introduces new bits in *status for recording landing pad state and a new exception type `software check exception` with cause=0x12. Link: https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Reviewed-by: Atish Patra Reviewed-by: Samuel Holland

lib: sbi: fwft: add support for SBI_FWFT_POINTER_MASKING_PMLEN

2024-09-23T12:20:40Z

Add support for controlling the pointer masking mode on harts which support the Smnpm extension. This extension can only exist on harts where XLEN >= 64 bits. This implementation selects the mode with the smallest PMLEN that satisfies the caller's requested lower bound. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: sbi: Enhance CSR Handling in system_opcode_insn

2024-08-23T08:06:49Z

- Completed TODO in `system_opcode_insn` to ensure CSR read/write instruction handling. - Refactored to use new macros `GET_RS1_NUM` and `GET_CSR_NUM`. - Updated `GET_RM` macro and replaced hardcoded funct3 values with constants (`CSRRW`, `CSRRS`, `CSRRC`, etc.). - Removed redundant `GET_RM` from `riscv_fp.h`. - Improved validation and error handling for CSR instructions. This patch enhances the clarity and correctness of CSR handling in `system_opcode_insn`. Signed-off-by: Dongdong Zhang Reviewed-by: Anup Patel

include: Adjust Sscofpmf mhpmevent mask for upper 8 bits

2024-08-02T03:13:27Z

Currently, OpenSBI reserves the upper 16 bits in mhpmevent for the Sscofpmf extension. However, according to the Sscofpmf extension specification[1], it only defines the upper 8 bits in mhpmevent for privilege mode inhibit and counter overflow disable. Other bits are defined by the platform for event selection. Since vendors might define raw event encoding exceeding 48 bits in mhpmevent, we should adjust the MHPMEVENT_SSCOF_MASK to support it. Link: https://github.com/riscvarchive/riscv-count-overflow [1] Signed-off-by: Eric Lin Reviewed-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Add support for Svade and Svadu extensions

2024-06-18T11:11:32Z

Add support for Svade and Svadu extensions. When both are present in the device tree, the M-mode firmware should select the Svade extension to comply with the RVA23 profile, which mandates Svade and lists Svadu as an optional extension. Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel