opensbi.git/include/sbi/riscv_encoding.h, branch v1.7

lib: Emulate AMO instructions when Zaamo is not available

2025-05-20T03:48:03Z

The AMO instructions are very critical for Linux so allow low-end RISC-V implementations without Zaamo to boot Linux by emulating AMO instructions using Zalrsc when OpenSBI is compiled without Zaamo. Signed-off-by: Chao-ying Fu Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20250519121207.976949-1-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: sbi: Enable Control Transfer Records (CTR) Ext using xstateen.

2025-04-13T00:41:43Z

The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and the latest release can be found here https://github.com/riscv/riscv-control-transfer-records/release Signed-off-by: Rajnesh Kanwal Reviewed-by: Atish Patra Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250307124451.122828-1-rkanwal@rivosinc.com Signed-off-by: Anup Patel

lib: sbi_trap: Add support for vectored interrupts

2025-04-13T00:21:17Z

When redirecting an exception to S-mode, transform the (v)stvec CSR value as described in the privileged spec to derive the S-mode PC. Since OpenSBI never redirects interrupts, only synchronous exceptions, the only action needed is to mask out the (v)stvec.MODE field. Reported-by: Jan Reinhard Closes: https://github.com/riscv-software-src/opensbi/issues/391 Signed-off-by: Samuel Holland Reviwed-by: Anup Patel Link: https://lore.kernel.org/r/20250305014729.3143535-1-samuel.holland@sifive.com Signed-off-by: Anup Patel

lib: sbi: sse: Add support for SSTATUS.SDT

2025-03-27T12:46:44Z

Similarly to what is done for SPELP, handle SSTATUS.SDT upon event injection. In order to mimick an interrupt, set SDT to 1 for injection and save its previous value in interrupted_flags[5:5]. Restore it upon completion. Signed-off-by: Clément Léger Reviewed-by: Andrew Jones

lib: sbi_misaligned_ldst: Add handling of vector load/store

2024-12-06T12:13:06Z

Add misaligned load/store handling for the vector extension to the sbi_misaligned_ldst library. This implementation is inspired from the misaligned_vec_ldst implementation in the riscv-pk project. Co-developed-by: Zong Li Signed-off-by: Zong Li Signed-off-by: Nylon Chen Reviewed-by: Andy Chiu Reviewed-by: Anup Patel

lib: sbi: add Smdbltrp ISA extension support

2024-10-25T18:30:12Z

Add support for the Smdbltrp[1] ISA extension. First thing to do is clearing MDT on entry after setting the first MTVEC (since MDT is reset to 1). Additionally, during trap handling, clear MDT once all critical CSRs have been saved and in return path, restore MSTATUS/H before restoring MEPC to avoid taking another trap which would clobber it. Link: https://github.com/riscv/riscv-double-trap/releases/download/v0.56/riscv-double-trap.pdf [1] Signed-off-by: Clément Léger Reviewed-by: Samuel Holland

lib: sbi: implement firmware feature SBI_FWFT_DOUBLE_TRAP

2024-10-25T18:29:27Z

Add support for double trap firmware feature. Link: https://lists.riscv.org/g/tech-prs/message/985 [1] Signed-off-by: Clément Léger Reviewed-by: Samuel Holland

lib: sbi: fwft: factorize menvcfg read/write

2024-10-25T18:28:58Z

MENVCFG access will be used as well for double trap, landing pad and shadow stack fwft support. Factorize that in a common function. Signed-off-by: Clément Léger Reviewed-by: Samuel Holland

lib: sbi: add Ssdbltrp ISA extension support

2024-10-25T18:28:00Z

Add Ssdbltrp trap handler support for S-mode double trap handling. If the trap is received while in VS-mode, then the trap is redirected to S-mode. If caught while in HS-mode, then an error is returned to the top trap handler which will panic. Signed-off-by: Clément Léger Reviewed-by: Samuel Holland

include: adding support for Zicfilp / Zicfiss encodings

2024-09-23T13:25:07Z

Zicfilp / Zicfiss extension (see link) introduces b2 (LPE) in menvcfg CSR to enable landing pads and b3 (SSE) in menvcfg CSR to enable shadow stack and landing pad for privilege less than M. Additionally extension introduces new bits in *status for recording landing pad state and a new exception type `software check exception` with cause=0x12. Link: https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Reviewed-by: Atish Patra Reviewed-by: Samuel Holland