opensbi.git/include/sbi/riscv_encoding.h, branch v1.8

include: sbi: Ignore rs1 and rd fields in FENCE.TSO.

2025-12-15T13:12:00Z

While FENCE.TSO is only specified with them set to zero, it is a special case of FENCE, which needs to ignore these otherwise reserved fields, but in some implementations, namely XuanTie C906 and C910, apparently does not. See the RISCVuzz paper by Thomas et al. for details. Signed-off-by: Benedikt Freisen Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114203842.13396-5-b.freisen@gmx.net Signed-off-by: Anup Patel

include: sbi: Fix tab alignment.

2025-12-15T13:12:00Z

A previous editor or formatter script appears to have been confused by a diff view, where the prepended + or - changes the way tabs are displayed. Since it is the file itself that matters, adjust that accordingly. Signed-off-by: Benedikt Freisen Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114203842.13396-4-b.freisen@gmx.net Signed-off-by: Anup Patel

lib: sbi: Enable Ssqosid Ext using mstateen0

2025-12-08T05:34:06Z

The QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers. If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception. This extension can be found in the RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual Changes in v5: - Remove SBI_HART_EXT_SSQOSID dependency SBI_HART_PRIV_VER_1_12 Changes in v4: - Remove extraneous parentheses around SMSTATEEN0_SRMCFG Changes in v3: - Check SBI_HART_EXT_SSQOSID when swapping SRMCFG Changes in v2: - Remove trap-n-detect - Context switch CSR_SRMCFG Signed-off-by: Chen Pei Reviewed-by: Radim Krčmář Link: https://lore.kernel.org/r/20251114115722.1831-1-cp0613@linux.alibaba.com Signed-off-by: Anup Patel

lib: Allow custom CSRs in csr_read_num() and csr_write_num()

2025-10-21T14:04:09Z

Some of the platforms use platform specific CSR access functions for configuring implementation specific CSRs (such as PMA registers). Extend the common csr_read_num() and csr_write_num() to allow custom CSRs so that platform specific CSR access functions are not needed. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com Signed-off-by: Anup Patel

include: sbi: Remove unused (LOG_)REGBYTES

2025-07-22T10:24:27Z

These are no longer used, so remove them. Signed-off-by: Jessica Clarke Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250709232932.37622-3-jrtc27@jrtc27.com Signed-off-by: Anup Patel

include: sbi: Use array for struct sbi_trap_regs and GET/SET macros

2025-07-22T10:24:27Z

Rather than hand-rolling scaled pointer arithmetic with casts and shifts, let the compiler do so by indexing an array of GPRs, taking advantage of the language's type system to scale based on whatever type the register happens to be. This makes it easier to support CHERI where the registers are capabilities, not plain integers, and so this pointer arithmetic would need to change (and currently REGBYTES is both the size of a register and the size of an integer word upstream). Signed-off-by: Jessica Clarke Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250709232932.37622-1-jrtc27@jrtc27.com Signed-off-by: Anup Patel

lib: Emulate AMO instructions when Zaamo is not available

2025-05-20T03:48:03Z

The AMO instructions are very critical for Linux so allow low-end RISC-V implementations without Zaamo to boot Linux by emulating AMO instructions using Zalrsc when OpenSBI is compiled without Zaamo. Signed-off-by: Chao-ying Fu Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20250519121207.976949-1-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: sbi: Enable Control Transfer Records (CTR) Ext using xstateen.

2025-04-13T00:41:43Z

The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and the latest release can be found here https://github.com/riscv/riscv-control-transfer-records/release Signed-off-by: Rajnesh Kanwal Reviewed-by: Atish Patra Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250307124451.122828-1-rkanwal@rivosinc.com Signed-off-by: Anup Patel

lib: sbi_trap: Add support for vectored interrupts

2025-04-13T00:21:17Z

When redirecting an exception to S-mode, transform the (v)stvec CSR value as described in the privileged spec to derive the S-mode PC. Since OpenSBI never redirects interrupts, only synchronous exceptions, the only action needed is to mask out the (v)stvec.MODE field. Reported-by: Jan Reinhard Closes: https://github.com/riscv-software-src/opensbi/issues/391 Signed-off-by: Samuel Holland Reviwed-by: Anup Patel Link: https://lore.kernel.org/r/20250305014729.3143535-1-samuel.holland@sifive.com Signed-off-by: Anup Patel

lib: sbi: sse: Add support for SSTATUS.SDT

2025-03-27T12:46:44Z

Similarly to what is done for SPELP, handle SSTATUS.SDT upon event injection. In order to mimick an interrupt, set SDT to 1 for injection and save its previous value in interrupted_flags[5:5]. Restore it upon completion. Signed-off-by: Clément Léger Reviewed-by: Andrew Jones