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<title>opensbi.git/include/sbi/sbi_ecall_interface.h, branch v1.4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/include/sbi/sbi_ecall_interface.h?h=v1.4</id>
<link rel='self' href='http://cgit.235523.xyz/opensbi.git/atom/include/sbi/sbi_ecall_interface.h?h=v1.4'/>
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<updated>2023-12-08T17:20:21Z</updated>
<entry>
<title>lib: sbi_pmu: Add PMU snapshot definitions</title>
<updated>2023-12-08T17:20:21Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2023-12-07T22:23:49Z</published>
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<id>urn:sha1:ee725174bada254f8a081937d870feb837618d6e</id>
<content type='text'>
OpenSBI doesn't support SBI PMU snapshot yet as there is not much benefit
unless the multiple counters overflow at the same time.

Just add the definition and return not supported error at this moment. The
default returned error is also not supported. Thus, no functional change
intended.

Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Align the event type offset as per SBI specification</title>
<updated>2023-04-07T04:36:59Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-03-30T08:41:14Z</published>
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<id>urn:sha1:edc9914392791031df624a7c79d1706f83199666</id>
<content type='text'>
The bits encoded in event_idx[19:16] indicate the event type, with
an offset of 16 instead of 20.

Fixes: 13d40f21d588 ("lib: sbi: Add PMU support")
Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>include: Add defines for SBI CPPC extension</title>
<updated>2023-04-07T04:05:06Z</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2023-03-29T08:57:25Z</published>
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<id>urn:sha1:45ba2b203cc38ebfd634dc42c1dd3a2d380a8899</id>
<content type='text'>
Add SBI CPPC extension related defines to the
SBI ecall interface header.

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Reserve space for implementation specific firmware events</title>
<updated>2023-03-10T08:30:22Z</updated>
<author>
<name>Mayuresh Chitale</name>
<email>mchitale@ventanamicro.com</email>
</author>
<published>2023-03-09T13:13:53Z</published>
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<id>urn:sha1:60c358e6774847629cd608a8841c4e7752b4949a</id>
<content type='text'>
We reserve space for SBI implementation specific custom firmware
events which can be used by M-mode firmwares and HS-mode hypervisors
for their own use. This reserved space is intentionally large to
ensure that SBI implementation has enough space to accommodate
platform specific firmware events as well.

Signed-off-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi</title>
<updated>2023-03-10T08:30:07Z</updated>
<author>
<name>Mayuresh Chitale</name>
<email>mchitale@ventanamicro.com</email>
</author>
<published>2023-03-09T13:13:52Z</published>
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<id>urn:sha1:51951d9e9af86c885cf5564bba7dd83a9a59a3b3</id>
<content type='text'>
To support 64 bit firmware counters on RV32 systems, we implement
sbi_pmu_counter_fw_read_hi() which returns the upper 32 bits of
the firmware counter value. On RV64 (or higher) systems, this
function will always return zero.

Signed-off-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add system suspend skeleton</title>
<updated>2023-02-27T14:13:52Z</updated>
<author>
<name>Andrew Jones</name>
<email>ajones@ventanamicro.com</email>
</author>
<published>2023-02-27T10:31:02Z</published>
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<id>urn:sha1:73623a0acac7f62646757cdd5a03b325eba3e0c9</id>
<content type='text'>
Add the SUSP extension probe and ecall support, but for now the
system suspend function is just a stub.

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: Add defines for SBI debug console extension</title>
<updated>2023-02-09T16:51:24Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-07-22T10:55:51Z</published>
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<id>urn:sha1:e3bf1afcc568fece971d67395f63461fddb4c0fa</id>
<content type='text'>
We add SBI debug console extension related defines to the
SBI ecall interface header.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add the bound check for events during config match</title>
<updated>2022-07-30T05:52:50Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2022-07-20T21:50:33Z</published>
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<id>urn:sha1:83db3af5f93dbbffb599af41c58e26a24b1abc1c</id>
<content type='text'>
Currently, there is no sanity check for firmware event code. We don't see
any issue as Linux kernel driver does a bound check on firmware events
already. However, OpenSBI can't assume sane supervisor mode software
always. Thus, an invalid event idx can cause a buffer overflow error.
For hardware events, the match will fail for invalid event code anyways.
However, a search is unecessary if event code is invalid.

Add a event ID validation function to solve the issue.

Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add PMU support</title>
<updated>2021-07-11T04:53:18Z</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2021-07-10T16:18:11Z</published>
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<id>urn:sha1:13d40f21d588e17a31624ed415f114987b6bd3d0</id>
<content type='text'>
RISC-V SBI v0.3 specification defined a PMU extension to configure/start/stop
the hardware/firmware pmu events.

Implement PMU support in OpenSBI library. The implementation is agnostic of
event to counter mapping &amp; mhpmevent value configuration. That means, it
expects platform hooks will be used to set up the mapping and provide
the mhpmevent value at runtime.

Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: sbi: SBI function IDs for RFENCE extension</title>
<updated>2021-03-12T04:02:53Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2021-03-09T11:31:22Z</published>
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<id>urn:sha1:ff5bd949d55b14e1d308288ace71366b090f822d</id>
<content type='text'>
The SBI function IDs for RFENCE extension must match the SBI specification.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
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