opensbi.git/include/sbi/sbi_hfence.h, branch master

lib: sbi: Fix GPA passed to __sbi_hfence_gvma_xyz() functions

2021-11-02T10:32:08Z

The parameter passed to HFENCE.GVMA instruction in rs1 register is guest physical address right shifted by 2 (i.e. divided by 4). Unfortunately, we overlooked the semantics of rs1 registers for HFENCE.GVMA instruction and never right shifted guest physical address by 2. This issue did not manifest for hypervisors till now because all H-extension implementations (such as QEMU, Spike, Rocket Core FPGA, etc) we tried till now were conservatively flushing everything upon any HFENCE.GVMA instruction. This patch fixes GPA passed to __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_gvma_gpa() functions. Fixes: 331ff6a162c1 ("lib: Support stage1 and stage2 tlb flushing") Reported-by: Ian Huang Signed-off-by: Anup Patel Reviewed-by: Xiang W Reviewed-by: Dong Du

lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va()

2020-06-15T03:54:27Z

The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va() functions are swapped so we fix it. Currently, we did not face any issues because QEMU does a full TLB flush for all HFENCE instructions. We also improve documentation of HFENCE.GVMA and HFENCE.VVMA instruction encoding. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Add hfence instruction encoding

2019-12-23T03:42:16Z

Currently, the toolchains do not have support for hfence instruction. Hence, the instruction are hardcode until we have toolchain support. Signed-off-by: Atish Patra Reviewed-by: Anup Patel