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<title>opensbi.git/include/sbi/sbi_misaligned_ldst.h, branch v1.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2020-03-28T08:02:14Z</updated>
<entry>
<title>lib: sbi_misaligned_ldst: Remove mcause, scratch and hartid parameters</title>
<updated>2020-03-28T08:02:14Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-03-19T16:00:02Z</published>
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<id>urn:sha1:fe37d7da29f67ae8ccc31f06e0f3e6c9a6b58054</id>
<content type='text'>
We remove mcause, scratch and hartid parameters from various functions
for misaligned load/store handling because we can always get current
HART id and current scratch pointer using just one CSR access.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Extend trap redirection for hypervisor v0.5 spec</title>
<updated>2019-12-16T09:18:26Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2019-12-12T16:53:30Z</published>
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<id>urn:sha1:2be424bd28560d5399788ed16f663f7785a8c5f9</id>
<content type='text'>
The hypervisor v0.5 spec introduces two new CSRs for both M-mode
and HS-mode which need to be considered when redirecting traps
hence this patch.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>all: Update copyright header in all files</title>
<updated>2019-01-24T08:37:47Z</updated>
<author>
<name>Anup patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2019-01-24T06:11:10Z</published>
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<id>urn:sha1:20990ee0abaf286917b6e2aae992d4183ff695f6</id>
<content type='text'>
This patch updates copyright header in all files as follows:
1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line
2. Change copyright year to 2019 for Western Digital

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Add misaligned load/store trap handling</title>
<updated>2018-12-26T05:44:22Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2018-12-24T11:19:01Z</published>
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<id>urn:sha1:b5ae8e8a650d8cb0134f03f53472fb026d2ee6e6</id>
<content type='text'>
We generally don't get misaligned load/store traps from Linux/U-Boot
compiled using GCC 8.2 or higher but this is not true with older
GCC toolchains. To tackle this we add misaligned load/store trap
handling adopted from BBL sources but much more simpler.
(Note: BBL sources can be found at https://github.com/riscv/riscv-pk.git)

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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