opensbi.git/include/sbi/sbi_platform.h, branch master

lib: sbi: Make per-HART stack size configurable via Kconfig

2026-06-16T13:51:11Z

The per-HART stack size for exception/interrupt handling is currently hardcoded to 8192 bytes in SBI_PLATFORM_DEFAULT_HART_STACK_SIZE. This may not be sufficient for platforms with deeper call stacks (e.g. those enabling additional SBI extensions) or may be wasteful for minimal platforms. Introduce a HART_STACK_SIZE Kconfig option in lib/sbi/Kconfig with a valid range of 8192 to 1048576 bytes and a default of 8192 bytes to preserve existing behavior. The SBI_PLATFORM_DEFAULT_HART_STACK_SIZE macro now resolves to CONFIG_HART_STACK_SIZE, allowing all platforms to benefit from a single configuration knob without any source changes. Signed-off-by: Oriol Catalan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/VI0P192MB3062735A6194BB6DA72083499E002@VI0P192MB3062.EURP192.PROD.OUTLOOK.COM Signed-off-by: Anup Patel

lib: sbi: Do not override emulator callback for vector load/store

2026-06-16T07:55:27Z

It's wrong to override the emulator callback in sbi_trap_emulate_load/ store. The function must respect the callback function passed in the parameter. Hence, let the misaligned emulator callback decide when to use sbi_misaligned_v_ld/st_emulator. To clean up things, also make the following changes: - Add the `insn` parameter to the callback. The trapping insn has been fetched by the caller already, whether transformed or directly loaded, thus saving the trouble in the callback. Note that you must not rely on the length of the `insn`, as it can be a transformed one from tinst - Also the `tcntx` is added, providing the callback with register values to handle vector insn or other customized insns. - Clarify that the read/write length (rlen/wlen) can be 0, in which case it could be a vector load/store or some customized instruction. The callback is responsible to handle it accordingly. Also fixed issues in the sbi_misaligned_v_ld/st_emulator: a. Redirect the trap when OPENSBI_CC_SUPPORT_VECTOR is not available. b. Ensure the return code is >0 when no faults are redirected. Fixes: c2acc5e5b0d8 ("lib: sbi_misaligned_ldst: Add handling of vector load/store") Signed-off-by: Bo Gan Reviewed-by: Anup Patel Tested-by: Anirudh Srinivasan Link: https://lore.kernel.org/r/20260605113214.242-6-ganboing@gmail.com Signed-off-by: Anup Patel

platform: generic: Optimize extensions_init() to parse ISA extensions once

2026-06-12T10:38:29Z

Instead of parsing ISA extensions separately for each hart in the generic_extensions_init() function, it is better to parse ISA extensions for all available harts in the cold boot path. Also, this allows us to remove fdt_isa_bitmap from scratch space and directly initialize "extensions" in struct sbi_hart_features for each hart. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260521082625.1520870-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi: hart: Detect and enable Smrnmi before trap-based feature detection

2026-05-09T07:29:43Z

The location of the RNMI/E trap vectors in the Smrnmi extension is implementation-defined, so platforms with vendor-specific NMI vector mechanisms must install the firmware's NMI entry points themselves. Add an smrnmi_handlers_init() callback to sbi_platform_operations that receives the firmware entry points and lets platform code install them at the hardware-specific vector locations. Two pointers are passed: - _trap_rnmi_handler: the dedicated RNMI entry point that saves context using the Smrnmi MN* CSRs and returns via mnret. - _trap_handler: the regular M-mode trap entry since RNME is taken as a regular M-mode trap with NMIE=0. When Smrnmi is present, install the platform's NMI vectors via the new callback, initialize MNSCRATCH with the per-hart scratch pointer, and set MNSTATUS.NMIE. Smrnmi-enabled platforms must register smrnmi_handlers_init; if the extension is detected but no callback is registered, sbi_panic() is called since enabling NMIs without handlers in place would route subsequent traps into nowhere. Signed-off-by: Evgeny Voevodin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/88b1470e1e3348d454b4b995a11a85c01914f7af.1778176768.git.evvoevod@tenstorrent.com Signed-off-by: Anup Patel

firmware: Add RNMI handler infrastructure

2026-05-09T07:29:43Z

Implement basic Resumable NMI (RNMI) handler support for the RISC-V Smrnmi extension. The new _trap_rnmi_handler assembly entry point saves context using the Smrnmi MN* CSRs (MNSCRATCH, MNEPC, MNSTATUS, MNCAUSE) and returns via mnret. It dispatches to sbi_trap_rnmi_handler(), which optionally calls a platform-specific ops->rnmi_handler callback for actual NMI processing. If no platform handler is registered or it fails, the event is reported as an unhandled NMI. The RNMI handler reuses the generic trap context structure but stores MN* CSR values (MNEPC, MNSTATUS, MNCAUSE) into the corresponding generic fields (mepc, mstatus, cause) for compatibility with existing trap infrastructure. Signed-off-by: Evgeny Voevodin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/050ae6d2762ba8d5b9dfb3cc1960a23aa3d6c549.1778176768.git.evvoevod@tenstorrent.com Signed-off-by: Anup Patel

lib: sbi: give platform choice of using single memregion to cover OpenSBI

2025-12-21T15:03:23Z

By default the OpenSBI itself is covered by 2 memregions for RX/RW sections. This is required by platforms with Smepmp to enforce proper permissions in M mode. Note: M-mode only regions can't have RWX permissions with Smepmp. Platforms with traditional PMPs won't be able to benefit from it, as both regions are effectively RWX in M mode, but usually it's harmless to so. Now we provide these platforms with an option to disable this logic. It saves 1 PMP entry. For platforms really in short of PMPs, it does make a difference. Note: Platform requesting single OpenSBI memregion must be using traditional (old) PMP. We expect the platform code to do the right thing. Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251218104243.562667-5-ganboing@gmail.com Signed-off-by: Anup Patel

include: sbi: Remove platform specific IPI init

2025-09-16T04:26:31Z

The platform specfic IPI init is not need anymore because using IPI device rating multiple IPI devices can be registered in any order as part of the platform specific early init. Signed-off-by: Anup Patel Reviewed-by: Samuel Holland Tested-by: Nick Hu Link: https://lore.kernel.org/r/20250904052410.546818-3-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: sbi_platform: Add platform specific pmp_set() and pmp_disable()

2025-06-17T04:04:01Z

Allow platforms to implement platform specific PMP setup and PMP disable functions which are called before actual PMP CSRs are configured. Also, implement pmp_set() and pmp_disable() for MIPS P8700. Signed-off-by: Chao-ying Fu Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20250614172756.153902-1-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: sbi: Set the scratch allocation to alignment to cacheline size

2025-04-24T03:53:47Z

Set the scratch allocation alignment to cacheline size specified by riscv,cbom-block-size in the DTS file to avoid two atomic variables from the same cache line causing livelock on some platforms. If the cacheline is not specified, we set it a default value. Signed-off-by: Raj Vishwanathan Reviewed-by: Anup Patel Reviewed-by: Samuel Holland Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com Signed-off-by: Anup Patel

lib: sbi_platform: Remove the vendor_ext_check hook

2025-04-23T07:02:51Z

Now that the generic platform only sets .vendor_ext_provider if the function is really implemented, there is no need for a separate hook to check if a vendor extension is implemented. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250325234342.711447-11-samuel.holland@sifive.com Signed-off-by: Anup Patel