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<title>opensbi.git/include/sbi/sbi_platform.h, branch v1.7</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/include/sbi/sbi_platform.h?h=v1.7</id>
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<updated>2025-06-17T04:04:01Z</updated>
<entry>
<title>lib: sbi_platform: Add platform specific pmp_set() and pmp_disable()</title>
<updated>2025-06-17T04:04:01Z</updated>
<author>
<name>Chao-ying Fu</name>
<email>cfu@wavecomp.com</email>
</author>
<published>2025-06-14T17:27:56Z</published>
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<id>urn:sha1:13abda516928a8823e6b7b65b0a29bb338484227</id>
<content type='text'>
Allow platforms to implement platform specific PMP setup and
PMP disable functions which are called before actual PMP CSRs
are configured.

Also, implement pmp_set() and pmp_disable() for MIPS P8700.

Signed-off-by: Chao-ying Fu &lt;cfu@mips.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20250614172756.153902-1-apatel@ventanamicro.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Set the scratch allocation to alignment to cacheline size</title>
<updated>2025-04-24T03:53:47Z</updated>
<author>
<name>Raj Vishwanathan</name>
<email>raj.vishwanathan@gmail.com</email>
</author>
<published>2025-04-23T22:50:45Z</published>
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<id>urn:sha1:99aabc6b8431a2bcf2b28a2423952e529de9fbc5</id>
<content type='text'>
Set the scratch allocation alignment to cacheline size specified by
riscv,cbom-block-size in the DTS file to avoid two atomic variables
from the same cache line causing livelock on some platforms. If the
cacheline is not specified, we set it a default value.

Signed-off-by: Raj Vishwanathan &lt;Raj.Vishwanathan@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_platform: Remove the vendor_ext_check hook</title>
<updated>2025-04-23T07:02:51Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2025-03-25T23:43:33Z</published>
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<id>urn:sha1:2b09a987010865f37508897f01024c0e6e408169</id>
<content type='text'>
Now that the generic platform only sets .vendor_ext_provider if the
function is really implemented, there is no need for a separate hook to
check if a vendor extension is implemented.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250325234342.711447-11-samuel.holland@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Simplify structure member offset checking</title>
<updated>2025-04-15T05:56:36Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2025-03-19T12:39:13Z</published>
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<id>urn:sha1:169b4b8ae2f3f1b337179a176a299284d0bed4fe</id>
<content type='text'>
Add a macro assert_member_offset() to perform structure member offset
checking.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250319123919.505443-1-wxjstz@126.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Use sbi_hart_count() and sbi_for_each_hartindex()</title>
<updated>2025-03-24T12:27:20Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2025-02-20T18:42:30Z</published>
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<id>urn:sha1:949c83a799e91cb57903932a84ec63fd14de5dc6</id>
<content type='text'>
Simplify the code and improve consistency by using the new macros where
possible. sbi_hart_count() obsoletes sbi_scratch_last_hartindex().

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_scratch: Apply bounds check to platform hart_count</title>
<updated>2025-03-24T12:26:04Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2025-02-20T18:42:27Z</published>
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<id>urn:sha1:ef4ed2dda76648171d551537443a16b5db712284</id>
<content type='text'>
The internal limit on the number of harts is SBI_HARTMASK_MAX_BITS, as
this value determines the size of various bitmaps and arrays (including
hartindex_to_hartid_table and hartindex_to_scratch_table). Clamp the
value provided by the platform, and drop the extra array element.

Update the documentation to indicate that hart_index2id must be sized
based on hart_count, and that hart indexes must be contiguous. As of
commit 5e90e54a1a53 ("lib: utils:Check that hartid is valid"), there is
no restriction on the valid hart ID values.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add SBI Message Proxy (MPXY) framework</title>
<updated>2024-12-06T03:56:50Z</updated>
<author>
<name>Rahul Pathak</name>
<email>rpathak@ventanamicro.com</email>
</author>
<published>2024-08-08T05:33:04Z</published>
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<id>urn:sha1:7939bf1329eb551845dbfa3ee06d92d30de70662</id>
<content type='text'>
Introduce SBI Message Proxy (MPXY) framework which allows platform specific
code or drivers to register message protocol specific channels.

This framework enables the supervisor software to send messages belonging
to different message protocols via OpenSBI firmware.

Signed-off-by: Rahul Pathak &lt;rpathak@ventanamicro.com&gt;
Co-developed-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Co-developed-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>platform: Drop irqchip warm init and exit hooks</title>
<updated>2024-11-28T06:16:36Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:09Z</published>
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<id>urn:sha1:678f5909a3fe54d528276f9afce5dd3148e42cbf</id>
<content type='text'>
Now that driver lifecycle is managed from within the SBI irqchip core,
platforms need only to initialize the driver once during cold init.
Remove the remaining platform hooks that are no longer used.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: Drop IPI warm init and exit hooks</title>
<updated>2024-11-11T12:51:04Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-10-25T18:59:48Z</published>
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<id>urn:sha1:86d2c1797a44975e628bcf77e30e687fd6738e81</id>
<content type='text'>
Now that the SBI IPI core clears IPIs at warm boot in a generic way,
none of the drivers or platforms use these hooks, and we can remove
them. Platforms need only to initialize the driver once during cold
init. If other hooks are needed in the future, they can be added to
struct sbi_ipi_device.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: ensure enough heap size with debug triggers extension</title>
<updated>2024-11-11T12:10:22Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@gmail.com</email>
</author>
<published>2024-11-11T02:27:33Z</published>
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<id>urn:sha1:dcb68dd17d21c80cbd340610c7eb16c33e83bf20</id>
<content type='text'>
DBTR introduce a big heap allocation to store hart state, this is
allocated percpu and needs big space when CPU number is high.

Increase the percpu part to fix this problem, and decrease the
fixed part to avoid too big heap size.

Fixes: 97f234f (lib: sbi: Introduce the SBI debug triggers extension support)
Signed-off-by: Inochi Amaoto &lt;inochiama@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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