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<title>opensbi.git/include/sbi/sbi_pmu.h, branch master</title>
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<updated>2026-02-21T04:50:41Z</updated>
<entry>
<title>lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64</title>
<updated>2026-02-21T04:50:41Z</updated>
<author>
<name>James Raphael Tiovalen</name>
<email>jamestiotio@gmail.com</email>
</author>
<published>2026-01-25T09:06:43Z</published>
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<id>urn:sha1:9656943bd3a2cad9418465c2a168f907ea52189b</id>
<content type='text'>
Currently, when we attempt to read the upper 32 bits of a firmware
counter on RV64 or higher, we just set `sbiret.value` to 0 without
validating the counter index. The SBI specification requires us to set
`sbiret.error` to `SBI_ERR_INVALID_PARAM` if the counter index points to
a hardware counter or an invalid counter. Add a validation check to
ensure compliance with the specification on RV64 or higher.

Fixes: 51951d9e9af8 ("lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi")
Signed-off-by: James Raphael Tiovalen &lt;jamestiotio@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260125090643.190748-1-jamestiotio@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: pmu: fix usage of sbi_pmu_irq_bit()</title>
<updated>2025-01-30T05:00:45Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2025-01-10T13:15:50Z</published>
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<id>urn:sha1:3943ddbaab00247b391128ae0a1f9258d4007f4f</id>
<content type='text'>
While sbi_pmu_irq_bit() was used to delegate irq to S-mode, LCOFIP usage
was still hardcoded in various places. This led to change the returned
value of sbi_pmu_irq_bit() to be a bit number rather than a bit mask
since it returns an 'int' and we need to obtain the bit number itself to
handle it in the IRQs handlers. Add a similar function to return the
irq mask which can also be used where the mask is required rather than
the bit itself.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Implement SBI PMU event info function</title>
<updated>2024-12-02T04:22:55Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-11-19T19:34:38Z</published>
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<id>urn:sha1:e4345842168b5725f56a81f1211d08f1a9d6c897</id>
<content type='text'>
Allow the supervisor software to query about the event using the
new function. This supports both firmware and hardware events.
The hardware event presence is verified hw_event_map which is populated
via PMU device tree node. The firmware event presence is checked through
event validation function which should take care of both standard and
platform firmware events.

Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add SSE support for PMU events</title>
<updated>2024-04-05T11:39:39Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-03-21T15:57:18Z</published>
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<id>urn:sha1:06fc453ec13de75e156261e8fe4073334d0e00c2</id>
<content type='text'>
Add SSE callbacks registration to PMU driver in order to disable
interrupt delegation for PMU interrupts. When interrupts are
undelegated send the PMU SSE event upon LCOFIP IRQ.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Fix the counter info function</title>
<updated>2023-12-08T17:20:23Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2023-12-07T22:23:50Z</published>
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<id>urn:sha1:11a0ba5d4bce74b2573091c5533717c2871191f1</id>
<content type='text'>
The counter info should only return valid hardware counters for the ones
set in the counter mask. Otherwise, it will report incorrect number of
hardware counters to the supervisor if the platform has discontiguous
counters.

Fixes: c744ed77b18c ("lib: sbi_pmu: Enable noncontigous hpm event and counters")
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device</title>
<updated>2023-12-06T12:00:01Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-11-30T12:42:02Z</published>
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<id>urn:sha1:a48f2cfd94d3be641b2b17eb3fa9090bed2d6cb8</id>
<content type='text'>
Add support for custom PMU extensions to set inhibit bits
on custom CSRs by introducing the PMU device callback
hw_counter_filter_mode(). This allows the perf tool to
restrict event counting under a specified privileged
mode by appending a modifier, e.g. perf record -e event:k
to count events only happening in kernel mode.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Add hartid parameter PMU device ops</title>
<updated>2023-03-10T08:30:33Z</updated>
<author>
<name>Mayuresh Chitale</name>
<email>mchitale@ventanamicro.com</email>
</author>
<published>2023-03-09T13:13:58Z</published>
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<id>urn:sha1:c631a7da279e735590231d2ae432fbc05743aa9e</id>
<content type='text'>
Platform specific firmware event handler may leverage the hartid to program
per hart specific registers for a given counter.

Signed-off-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Introduce fw_counter_write_value API</title>
<updated>2023-03-10T08:30:30Z</updated>
<author>
<name>Mayuresh Chitale</name>
<email>mchitale@ventanamicro.com</email>
</author>
<published>2023-03-09T13:13:57Z</published>
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<id>urn:sha1:57d3aa3b0dbd534ab702dce61767df0e9dc7577f</id>
<content type='text'>
Add fw_counter_write_value API for platform specific firmware events
which separates setting the counter's initial value from starting the
counter. This is required so that the fw_event_data array can be reused
to save the event data received.

Signed-off-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: Update sbi_pmu dev ops</title>
<updated>2023-03-10T08:30:26Z</updated>
<author>
<name>Mayuresh Chitale</name>
<email>mchitale@ventanamicro.com</email>
</author>
<published>2023-03-09T13:13:55Z</published>
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<id>urn:sha1:b51ddffcc043fb94ebcbffce7682b2d0deef5afd</id>
<content type='text'>
Update fw_event_validate_code, fw_counter_match_code and fw_counter_start
ops which used a 32 bit event code to use the 64 bit event data instead.

Signed-off-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: add callback for counter width</title>
<updated>2023-03-10T08:16:52Z</updated>
<author>
<name>Mayuresh Chitale</name>
<email>mchitale@ventanamicro.com</email>
</author>
<published>2023-03-09T13:13:51Z</published>
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<id>urn:sha1:1fe8dc995566d869836d3caf37e427c28536f453</id>
<content type='text'>
This patch adds a callback to fetch the number of bits implemented for a
custom firmware counter. If the callback fails or is not implemented then
width defaults to 63.

Signed-off-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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