opensbi.git/include/sbi, branch master

lib: utils/mpxy: bind channel access to owning domain

2026-07-22T08:28:30Z

The MPXY framework currently stores registered channels in a global list and exposes them to all callers. However, the intended model is that each channel is assigned to a single supervisor domain at boot and remains owned by that domain for its lifetime. Introduce fixed owner-domain tracking in struct sbi_mpxy_channel and make channel lookup and enumeration domain-aware. A channel is now visible only when accessed from its owning domain. Also require the owner to be set before channel registration. This allows MPXY to support systems where the same hart may be reused by multiple domains while keeping channel ownership and visibility fixed to the domain that owns the service. Signed-off-by: Oza Pawandeep Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20260721215758.695736-1-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic: track IRQ enable state and restore EIE on warm init

2026-07-22T07:50:20Z

Add an irq_state field to struct sbi_irqchip_hwirq_data with a single IRQ_ENABLED flag (bit 0) to track whether a hardware interrupt has been enabled via the irqchip framework. Set IRQ_ENABLED in sbi_irqchip_unmask_hwirq() when the unmask callback is invoked. Add sbi_irqchip_get_irq_state() as a private inline accessor and expose sbi_irqchip_is_irq_enabled() as a public API for drivers to query the enabled state of a hardware interrupt by chip pointer and hwirq number. Refactor imsic_local_eix_update() to operate on a single interrupt ID instead of a base+count range, simplifying the CSR bit manipulation to a direct BIT(id) write without the inner loop. Update all call sites accordingly. Use sbi_irqchip_is_irq_enabled() in imsic_warm_irqchip_init() to restore per-EIID EIE CSR state on warm boot and HSM resume based on the saved irq_state, replacing the previous blanket disable of all interrupts. This ensures that EIIDs enabled during hotplug/warminit cycle are correctly re-enabled on the resuming hart without requiring software to re-register or re-unmask each interrupt. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-6-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent linking

2026-07-22T07:38:13Z

Add parent_unique_id fields to struct aplic_data for IMSIC parent linking in MSI mode. Store parent IMSIC unique_id during FDT parsing of the APLIC node. Add aplic_is_msi_mode() complementing aplic_is_direct_mode() to consolidate delivery mode detection. Add APLIC_TARGET_EIID() macro for packing the EIID field into the TARGET register. Add parent_unique_id and parent_irq_map fields to struct aplic_data. parent_unique_id identifies the upstream IMSIC irqchip device resolved via sbi_irqchip_find_device() during hwirq_setup. parent_irq_map is a per-source array allocated at cold init time to track the EIID assigned by the IMSIC for each APLIC source. Restore aplic_writel_msicfg() and re-introduce MSI address register programming in aplic_init(), gated on aplic_is_msi_mode(). Set the DOMAINCFG_DM bit to switch the hardware to MSI delivery mode when no IDC structures are present. Add aplic_program_msi_target() to pack hart_index, guest_index, and EIID into the APLIC_TARGET register. Add aplic_write_msi() as the sbi_irqchip write_msi callback that extracts EIID and hart_index from the MSI message and calls aplic_program_msi_target(). Add aplic_msi_callback() as the MSI receive callback that dispatches to sbi_irqchip_process_hwirq() on the APLIC chip. Extend aplic_hwirq_setup() with an MSI path that resolves the parent IMSIC chip by parent_unique_id, registers an MSI route via sbi_irqchip_register_msi(), and stores the allocated EIID in parent_irq_map for the source being configured. Extend aplic_hwirq_set_affinity() with an MSI path that delegates affinity reprogramming to the parent IMSIC chip via sbi_irqchip_set_affinity() using the stored parent_irq_map entry. Guard warm_init, process_hwirqs, and hwirq_eoi with early returns in MSI mode as interrupt delivery and acknowledgement are handled by the IMSIC in that configuration. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-3-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi: Move trap delegation setup to sbi_trap.c

2026-07-21T06:20:46Z

Currently, the trap delegation setup is part of sbi_hart.c and called via sbi_hart_init() whereas the per-hart trap (aka exception and interrupt) handling is part of sbi_trap.c. Move trap delegation init to sbi_trap.c and call it via new sbi_trap_init() from both cold boot and warm boot path. This way trap delegation setup is in same place as trap handling. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260613132129.2135128-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

include: Bump-up version to 1.9

2026-06-30T14:19:54Z

Update the OpenSBI version to 1.9 as part of release preparation. Signed-off-by: Anup Patel

lib: sbi: Rework misaligned vector load/store

2026-06-17T06:13:38Z

Fix the following issues with misaligned vector load/store: a. Stack overflow: the mask[VLEN_MAX / 8] variable consumes 8K stack space, given VLEN_MAX=65536, overflowing the default-sized stack. There's no need to fetch the whole mask in one go, instead, make it on-demand. Use a 128-byte mask as local buffer to hold the sliding window of mask. For rvv load, this is allowed -- from the spec: "The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction" We don't need to worry about the mask getting overwritten. b. Maintain the value of vstart upon abort (uptrap) to avoid duplicate work. After fault resolution, the instruction can restart from the faulting vstart. For Fault-Only-First loads, reset vstart to 0, as previously done so, to conform to spec. c. Explicitly set VS dirty in VSSTATUS with SET_VS_DIRTY() if faulting from V=1, and if any vector register, including vstart/vl/vtype, gets changed in the handler. It can add 1 unnecessary op to set VS dirty in M/SSTATUS (not VSSTATUS), where the HW already did, but for code simplicity, do it anyway. The overhead should be negligible. Signed-off-by: Bo Gan Tested-by: Anirudh Srinivasan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260609060024.706-5-ganboing@gmail.com Signed-off-by: Anup Patel

lib: sbi: Add variable-length unprivilege access functions

2026-06-17T06:11:11Z

sbi_load/store_loop read/write variable-length buffer unprivileged. Both function use the widest aligned 8/4/2/1 byte load/stores in each loop to reduce the total number of iterations. Also switch the scalar/vector misaligned handlers to make use of such functions to simplify code. Miscellaneous: remove the unnecessary [taddr] in inline assembly Signed-off-by: Bo Gan Tested-by: Anirudh Srinivasan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260609060024.706-4-ganboing@gmail.com Signed-off-by: Anup Patel

lib: sbi: Rework and split sbi_misaligned(_v)_tinst_fixup

2026-06-17T06:07:19Z

The load/store address offset between the uptrap and the orig_trap can be derived by orig_trap->tval - uptrap->tval, thus refactor the function prototype for simplicity. For vector load, sbi_misaligned_v_tinst_fixup is introduced. There's no transformed instruction for vector load/store, so null out tinst if the fault is not a guest-page fault. Signed-off-by: Bo Gan Tested-by: Anirudh Srinivasan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260609060024.706-3-ganboing@gmail.com Signed-off-by: Anup Patel

lib: sbi: Make per-HART stack size configurable via Kconfig

2026-06-16T13:51:11Z

The per-HART stack size for exception/interrupt handling is currently hardcoded to 8192 bytes in SBI_PLATFORM_DEFAULT_HART_STACK_SIZE. This may not be sufficient for platforms with deeper call stacks (e.g. those enabling additional SBI extensions) or may be wasteful for minimal platforms. Introduce a HART_STACK_SIZE Kconfig option in lib/sbi/Kconfig with a valid range of 8192 to 1048576 bytes and a default of 8192 bytes to preserve existing behavior. The SBI_PLATFORM_DEFAULT_HART_STACK_SIZE macro now resolves to CONFIG_HART_STACK_SIZE, allowing all platforms to benefit from a single configuration knob without any source changes. Signed-off-by: Oriol Catalan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/VI0P192MB3062735A6194BB6DA72083499E002@VI0P192MB3062.EURP192.PROD.OUTLOOK.COM Signed-off-by: Anup Patel

lib: sbi: Do not override emulator callback for vector load/store

2026-06-16T07:55:27Z

It's wrong to override the emulator callback in sbi_trap_emulate_load/ store. The function must respect the callback function passed in the parameter. Hence, let the misaligned emulator callback decide when to use sbi_misaligned_v_ld/st_emulator. To clean up things, also make the following changes: - Add the `insn` parameter to the callback. The trapping insn has been fetched by the caller already, whether transformed or directly loaded, thus saving the trouble in the callback. Note that you must not rely on the length of the `insn`, as it can be a transformed one from tinst - Also the `tcntx` is added, providing the callback with register values to handle vector insn or other customized insns. - Clarify that the read/write length (rlen/wlen) can be 0, in which case it could be a vector load/store or some customized instruction. The callback is responsible to handle it accordingly. Also fixed issues in the sbi_misaligned_v_ld/st_emulator: a. Redirect the trap when OPENSBI_CC_SUPPORT_VECTOR is not available. b. Ensure the return code is >0 when no faults are redirected. Fixes: c2acc5e5b0d8 ("lib: sbi_misaligned_ldst: Add handling of vector load/store") Signed-off-by: Bo Gan Reviewed-by: Anup Patel Tested-by: Anirudh Srinivasan Link: https://lore.kernel.org/r/20260605113214.242-6-ganboing@gmail.com Signed-off-by: Anup Patel