opensbi.git/include/sbi, branch v1.0

include: Bump-up version to 1.0

2021-12-24T11:57:44Z

This patch updates OpenSBI version to 1.0 as part of release preparation. Signed-off-by: Anup Patel

lib: pmu: support the event ID encoded by a bitmap.

2021-12-03T04:07:03Z

RISC-V privilege specification does not specify how to encode the event ID. Therefore, each platform is allowed to customize its own encoding rule. The common encoding methods are as follow, directly assigning a number to an event, or every bit in the mphmevent CSR controls one specified event or mixes the above two methods. To enable OpenSBI to support the above three encoding methods simultaneously, this patch repurpose the dt property "riscv,raw-event-to-mhpmcounters". The "riscv,raw-event-to-mhpmcounters" will describes the one or multiple raw events that could be counted by a set of counters. But, the column number of "riscv,raw-event-to-mhpmcounters" is extended from 2 to 3. The 1st column (64bit) is the ID of the raw events. The 2nd column (64bit) represents a select_mask now to represent the bits used for event ID encoding. If a platform directly encodes each raw PMU event as a unique ID, the value of select_mask will be 0xffffffff_ffffffff. Signed-off-by: Vincent Chen Signed-off-by: Atish Patra Reviewed-by: Anup Patel

lib: sbi: Improve fatal error handling

2021-12-02T03:20:36Z

BUG and BUG_ON are not informative and are rather lazy interfaces, only telling the user that something went wrong in a given function, but not what, requiring the user to find the sources corresponding to their firmware (which may not be available) and figure out how that BUG(_ON) was hit. Even SBI_ASSERT in its current form, which does include the condition that triggered it in the output, isn't necessarily very informative. In some cases, the error may be fixable by the user, but they need to know the problem in order to have any hope of fixing it. It's also a nuisance for developers, whose development trees may have changed significantly since the release in question being used, and so line numbers can make it harder for them to understand which error case a user has hit. This patch introduces a new sbi_panic function which is printf-like, allowing detailed error messages to be printed to the console. BUG and BUG_ON are removed, since the former is just a worse form of sbi_panic and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is augmented to take a set of arguments to pass to sbi_panic on failure, used like so (sbi_boot_print_hart's current error case, which currently manually calls sbi_printf and sbi_hart_hang): SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen)); The existing users of BUG are replaced with calls to sbi_panic along with informative error messages. BUG_ON and SBI_ASSERT were unused (and, in the case of SBI_ASSERT, remain unused). Many existing users of sbi_hart_hang should be converted to use either sbi_panic or SBI_ASSERT after this commit. Signed-off-by: Jessica Clarke Reviewed-by: Anup Patel Reviewed-by: Xiang W Reviewed-by: Atish Patra

lib: sbi: Allow programmable counters to monitor cycle/instret events

2021-11-11T12:18:45Z

A platform may use programmable counters for cycle/instret events. The priv spec allows that provided that cycle/instret also report those events in addition to the programmable counters. We should allow that functionality in OpenSBI. Reviewed-by: Anup Patel Reviewed-by: Bin Meng Signed-off-by: Atish Patra

lib: sbi: Support sscofpmf extension in OpenSBI

2021-11-11T12:16:57Z

This patch adds sscofpmf extension in pmu module which includes following things. 1. Enable overflow irq when starting a counter. 2. Setting the correct event filters passed from supervisor. 3. Delegating the overflow interrupt to the supervisor. 4. Add RV32 support for sscofpmf. Reviewed-by: Anup Patel Reviewed-by: Bin Meng Signed-off-by: Atish Patra

lib: sbi: Delegate PMU counter overflow interrupt to S mode

2021-11-11T12:15:12Z

OpenSBI doesn't handle PMU counters for now. Delegate the overflow counter to S-mode always. Reviewed-by: Bin Meng Reviewed-by: Anup Patel Signed-off-by: Atish Patra

lib: sbi: Detect Sscofpmf extension at run time

2021-11-11T12:12:59Z

Sscofpmf ISA extension introduces PMU counter overflow and filtering support. It introduces a read only `scountovf` csr that can be used to detect if a hart supports this extension at runtime. However, this feature is only useful if the hart already supports mcounteren and mcountinhibit. Add a dynamic detection mechanism and boot time print message if sscofpmf is present. Reviewed-by: Anup Patel Reviewed-by: Bin Meng Signed-off-by: Atish Patra

riscv: Add new CSRs introduced by Sscofpmf[1] extension

2021-11-11T12:07:34Z

[1] https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view Reviewed-by: Xiang W Reviewed-by: Bin Meng Reviewed-by: Anup Patel Signed-off-by: Atish Patra

lib: sbi: Fix GPA passed to __sbi_hfence_gvma_xyz() functions

2021-11-02T10:32:08Z

The parameter passed to HFENCE.GVMA instruction in rs1 register is guest physical address right shifted by 2 (i.e. divided by 4). Unfortunately, we overlooked the semantics of rs1 registers for HFENCE.GVMA instruction and never right shifted guest physical address by 2. This issue did not manifest for hypervisors till now because all H-extension implementations (such as QEMU, Spike, Rocket Core FPGA, etc) we tried till now were conservatively flushing everything upon any HFENCE.GVMA instruction. This patch fixes GPA passed to __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_gvma_gpa() functions. Fixes: 331ff6a162c1 ("lib: Support stage1 and stage2 tlb flushing") Reported-by: Ian Huang Signed-off-by: Anup Patel Reviewed-by: Xiang W Reviewed-by: Dong Du

lib: sbi: convert reset to list

2021-10-11T04:29:29Z

To support different handlers for different types of resets, we are adding a sbi_list of restart handlers. Instead of sbi_system_reset_set_device we use sbi_system_reset_add_device to reflect the actual meaning. Signed-off-by: Nikita Shubin Reviewed-by: Anup Patel