opensbi.git/include/sbi_utils/fdt, branch v1.2

lib: utils: serial: Add FDT driver for Renesas SCIF

2022-12-12T13:20:35Z

Add FDT driver for Renesas SCIF. dts example: soc: soc { .... scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, <414 IRQ_TYPE_LEVEL_HIGH>, <415 IRQ_TYPE_LEVEL_HIGH>, <413 IRQ_TYPE_LEVEL_HIGH>, <416 IRQ_TYPE_LEVEL_HIGH>, <416 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; clock-names = "fck"; power-domains = <&cpg>; resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; .... }; Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel

lib: utils/ipi: Add Andes fdt ipi driver support

2022-10-23T05:01:01Z

Move Andes PLICSW ipi device to fdt ipi framework, this patch is based on Leo's modified IPI scheme on PLICSW. Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according to spec. After some investigation, self-IPI seems to be seldom or never used, so we re-order the IPI scheme to support 8 core platforms. dts example (Quad-core AX45MP): plicsw: interrupt-controller@e6400000 { compatible = "andestech,plicsw"; reg = <0x00000000 0xe6400000 0x00000000 0x00400000>; interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 &CPU2_intc 3 &CPU3_intc 3>; interrupt-controller; #address-cells = <2>; #interrupt-cells = <2>; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: utils/timer: Add Andes fdt timer support

2022-10-23T04:56:39Z

Since we can get the PLMT base address and timer frequency from device tree, move plmt timer device to fdt timer framework. dts example (Quad-core AX45MP): cpus { ... timebase-frequency = <0x3938700>; ... } soc { ... plmt0@e6000000 { compatible = "andestech,plmt0"; reg = <0x00 0xe6000000 0x00 0x100000>; interrupts-extended = <&cpu0_intc 0x07 &cpu1_intc 0x07 &cpu2_intc 0x07 &cpu3_intc 0x07>; }; ... } Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: utils: serial: Add Cadence UART driver

2022-08-23T03:10:17Z

Add Cadence UART driver Signed-off-by: Jun Liang Tan Signed-off-by: Wei Liang Lim Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

lib: utils/fdt: Use kconfig for enabling/disabling

2022-08-08T04:04:08Z

We update FDT support makefile to use kconfig for enabling/disabling. To avoid compilation errors, we also enable FDT for each platform. Signed-off-by: Anup Patel Tested-by: Andrew Jones Acked-by: Atish Patra Tested-by: Atish Patra

lib: utils/fdt: Require match data to be const

2022-05-30T05:02:35Z

Match data stores hardware attributes which do not change at runtime, so it does not need to be mutable. Make it const. Reviewed-by: Guo Ren Reviewed-by: Xiang W Reviewed-by: Anup Patel Signed-off-by: Samuel Holland

lib: utils/fdt: rename fdt_parse_max_hart_id

2022-05-14T04:48:12Z

The function returns the highest hart-id of the harts actually used in the system (enabled). Change the name to reflect this fact. Signed-off-by: Jan Remes Reviewed-by: Anup Patel

lib: utils/fdt: introduce fdt_node_is_enabled()

2022-05-14T04:46:24Z

If an FDT node contains a "status" property and this property is not "ok" or "okay", this node should be ignored. Introduce a function that checks this. Signed-off-by: Jan Remes Reviewed-by: Xiang W Reviewed-by: Anup Patel

lib: utils/serial: support 'reg-offset' property

2022-04-17T08:27:48Z

reg-offset property is used for offset to apply to the mapbase from the start of the registers in 8250 UART. In Linux kernel, it has been handled in 8250 UART driver. dt-bindings: /Documentation/devicetree/bindings/serial/8250.yaml Signed-off-by: Zong Li Reviewed-by: Anup Patel

lib: utils: serial: Initial commit of xlnx-uartlite

2022-02-28T04:20:09Z

Initial commit of the xlnx-uartlite device and FDT support. This was tested by running OpenSBI on a modified QEMU virt machine using the xlnx-uartlite for serial. Signed-off-by: Alistair Francis Reviewed-by: Xiang W Reviewed-by: Anup Patel