opensbi.git/include/sbi_utils/ipi, branch v1.4

lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme

2023-12-06T11:53:27Z

The old scheme doesn't allow sending hart0 self-IPI as the corresponding bit on pending register is hardwired to 0, this could lead to unhandle IPIs on SMP systems, esp. on single-core. Furthermore, the limitation of old scheme is 8-core, instead of reserving source hart information, we assign bit (x + 1) as the enable and pending bit of hartx, this also expands the bootable hart number. The following diagram shows the enable bits of the new scheme on 32-core Andes platform. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> To send IPI to hart0, for example, another hart (including hart0 itself) will set bit 1 of first word on the pending register. We also fix indentation in andes_plicsw.h along with this patch. Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support") Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Randolph Reported-by: Lad Prabhakar Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

lib: utils/ipi: Add Andes fdt ipi driver support

2022-10-23T05:01:01Z

Move Andes PLICSW ipi device to fdt ipi framework, this patch is based on Leo's modified IPI scheme on PLICSW. Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according to spec. After some investigation, self-IPI seems to be seldom or never used, so we re-order the IPI scheme to support 8 core platforms. dts example (Quad-core AX45MP): plicsw: interrupt-controller@e6400000 { compatible = "andestech,plicsw"; reg = <0x00000000 0xe6400000 0x00000000 0x00400000>; interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 &CPU2_intc 3 &CPU3_intc 3>; interrupt-controller; #address-cells = <2>; #interrupt-cells = <2>; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: utils/ipi: Use kconfig for enabling/disabling drivers

2022-08-08T04:03:45Z

We update ipi drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate ipi drivers for each platform. Signed-off-by: Anup Patel Tested-by: Andrew Jones Acked-by: Atish Patra Tested-by: Atish Patra

lib: utils/ipi: Add ACLINT MSWI library

2021-06-24T04:09:44Z

We add common ACLINT MSWI library similar to the CLINT library so that OpenSBI platforms can use it. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Xiang W

lib: sbi: Simplify ipi platform operations

2021-04-28T11:33:31Z

Instead of having ipi_send() and ipi_clear() callbacks in platform operations, it will be much simpler for ipi driver to directly register these operations as a device to sbi_ipi implementation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis

lib: utils: Add simple FDT ipi framework

2020-05-01T04:28:01Z

We add simple ipi framework which will select and use ipi driver based on details in FDT passed by previous booting stage. Signed-off-by: Anup Patel Reviewed-by: Atish Patra