<feed xmlns='http://www.w3.org/2005/Atom'>
<title>opensbi.git/include/sbi_utils/irqchip, branch v1.7</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/include/sbi_utils/irqchip?h=v1.7</id>
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<updated>2025-02-12T15:52:37Z</updated>
<entry>
<title>lib: utils/irqchip: Use fdt_driver for initialization</title>
<updated>2025-02-12T15:52:37Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2025-01-19T19:03:55Z</published>
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<id>urn:sha1:9e1a1518d45968bb08f0996622ab25379135cf39</id>
<content type='text'>
The irqchip driver subsystem does not need any extra data, so it can use
`struct fdt_driver` directly. The generic fdt_irqchip_init() performs a
best-effort initialization of all matching DT nodes.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Fix irqchip registration for PLIC and APLIC</title>
<updated>2024-12-24T08:36:09Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-12-24T07:59:17Z</published>
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<id>urn:sha1:7150db29d7186808cc0df66b54dde1cb0ffe3535</id>
<content type='text'>
Currently, the same irqchip instance is registered for multiple PLIC
and APLIC instances which causes the sbi_list_for_each_entry() loop
in the sbi_irqchip_init() to hang at boot-time.

To address the above issue, register a separate irqchip instance for
each PLIC and APLIC instance.

Fixes: 2dd6eaf68055 ("lib: sbi_irqchip: Call driver warm_init from SBI core")
Reported-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>platform: Drop irqchip warm init and exit hooks</title>
<updated>2024-11-28T06:16:36Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:09Z</published>
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<id>urn:sha1:678f5909a3fe54d528276f9afce5dd3148e42cbf</id>
<content type='text'>
Now that driver lifecycle is managed from within the SBI irqchip core,
platforms need only to initialize the driver once during cold init.
Remove the remaining platform hooks that are no longer used.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Call driver warm_init from SBI core</title>
<updated>2024-11-28T06:10:17Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:08Z</published>
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<id>urn:sha1:2dd6eaf680556e763a85b0b4ae180391e2671854</id>
<content type='text'>
Currently, each platform keeps track of which irqchip driver is in use
and calls its warm init function. Since the generic platform may use
multiple irqchip drivers, it has logic to track an array of drivers.

The code is simplified and made common across platforms by treating warm
init and exit as properties of the driver, not the platform. Then the
platform's only role is to select and prepare a driver during cold boot.

For now, only add a .warm_init hook, since none of the existing drivers
need an .exit hook. It could be added in the future if needed.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Move per-hart data from fdt_plic to plic</title>
<updated>2024-11-28T06:05:01Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:06Z</published>
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<id>urn:sha1:56fddce83f163e5e90ea82bf78a8df3d990b0572</id>
<content type='text'>
The per-hart PLIC pointer is not really specific to FDT platforms. Move
it into the main driver and drop the extra wrapper functions.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Common PM save/restore</title>
<updated>2024-11-28T05:58:38Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=c6c22f00f457264560ca05414e9f9e0c5c3438db'/>
<id>urn:sha1:c6c22f00f457264560ca05414e9f9e0c5c3438db</id>
<content type='text'>
Move the PLIC save/restore functions inside the driver, so they can be
reused on any platform that needs them. The memory needed to store the
PLIC context is also allocated by the driver. The PM data cannot be
completely encapsulated, as some platforms (including Allwinner D1) need
to program the IRQ enable status to a sideband interrupt controller for
wakeup capability.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Provide a hartindex to context map</title>
<updated>2024-11-28T04:06:46Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=69448a07906523c9c798c8f1d02a7be52e96b38e'/>
<id>urn:sha1:69448a07906523c9c798c8f1d02a7be52e96b38e</id>
<content type='text'>
This removes platform-specific arguments to plic_warm_irqchip_init(),
which makes the driver independent from the platform after cold init,
and allows for further refactoring.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Move delegation to base PLIC driver</title>
<updated>2024-11-28T04:05:11Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=c26e3fd2ed655c1ae6efd1fd0cfc70360c1b967b'/>
<id>urn:sha1:c26e3fd2ed655c1ae6efd1fd0cfc70360c1b967b</id>
<content type='text'>
This needs to be in the base PLIC driver as part of the power management
save/restore flow.

This is also in preparation for moving the PLIC information in the
scratch area to the base PLIC driver. After that change, the FDT PLIC
layer will be unable to look up the `struct plic_data` after cold boot.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Allow enabling IRQs by default</title>
<updated>2024-11-28T04:05:10Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=a786aed08dbc20368426970eaf393867ec88b940'/>
<id>urn:sha1:a786aed08dbc20368426970eaf393867ec88b940</id>
<content type='text'>
Unlike other platforms, Ariane and OpenPiton enable all IRQs by default.
This was described in commit b44e844880d0 ("Add support for Ariane FPGA
SoC") as "due to some issue of the design." Add this workaround behind a
flag in plic_warm_irqchip_init(), so every platform can use the same
warm init function.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Look up IMSIC data by hart index</title>
<updated>2024-09-25T12:36:59Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-08-30T15:49:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=7f5fa9f9a48d3d4f6379ce207f50e8347cad3a14'/>
<id>urn:sha1:7f5fa9f9a48d3d4f6379ce207f50e8347cad3a14</id>
<content type='text'>
This avoids needing to map a hartid to a hart index.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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