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<title>opensbi.git/include/sbi_utils/serial, branch master</title>
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<updated>2026-02-20T11:20:35Z</updated>
<entry>
<title>lib: utils/serial: Add support for Altera JTAG UART</title>
<updated>2026-02-20T11:20:35Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>zhengxingda@iscas.ac.cn</email>
</author>
<published>2026-01-04T06:55:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=b07e449d15c534407391cb7b430117fefed084af'/>
<id>urn:sha1:b07e449d15c534407391cb7b430117fefed084af</id>
<content type='text'>
Altera provides a JTAG UART core that provides virtual UART over JTAG
and can coexist with their virtual JTAG. [1] This core has already been
supported by Linux and the programming interface has always been stable.

Add support for it to OpenSBI to ease JTAG prototype bringing up.

The driver follows the device tree binding in mainline Linux. [2]

[1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core
[2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml

Signed-off-by: Icenowy Zheng &lt;zhengxingda@iscas.ac.cn&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Support multiple UART8250 devices</title>
<updated>2025-12-21T15:32:44Z</updated>
<author>
<name>Bo Gan</name>
<email>ganboing@gmail.com</email>
</author>
<published>2025-12-18T10:42:42Z</published>
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<id>urn:sha1:fbff3a7e0784a5bd42e87656e6d50cea94dfcff5</id>
<content type='text'>
Previously we assume only 1 UART8250 instance can be used. Now we support
multiple instances by introducing counterpart functions to putc/getc/init
which take an extra *dev parameter, and name them as uart8250_device_xyz()
The original functions without the *dev parameter will operate on the
default instance exactly the same as before, so no changes on the caller
is required.

Note: uart8250_device_init only does device initialization without the
console registration logic.

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20251218104243.562667-7-ganboing@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Add PXA UARTs support</title>
<updated>2025-03-27T14:50:05Z</updated>
<author>
<name>Junhui Liu</name>
<email>junhui.liu@pigmoral.tech</email>
</author>
<published>2025-03-27T06:48:18Z</published>
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<id>urn:sha1:8fe835303c4c7d134f07002c234ec5ec637953ca</id>
<content type='text'>
The PXA variant of the uart8250 adds the UART Unit Enable bit (UUE) that
needs to be set to enable the XScale PXA UART. And it is required for
some RISC-V SoCs like the Spacemit K1 that implement the PXA UART.

This introduces the "intel,xscale-uart" compatible to handle setting the
UUE bit.

Signed-off-by: Junhui Liu &lt;junhui.liu@pigmoral.tech&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250327-pxa-uart-support-v2-1-c4400c1fcd0b@pigmoral.tech
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>inclue: sbi_utils: Cleanup int vs bool in semihosting_init() definitions</title>
<updated>2024-12-21T15:51:59Z</updated>
<author>
<name>Michael Neuling</name>
<email>michaelneuling@tenstorrent.com</email>
</author>
<published>2024-12-13T04:14:20Z</published>
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<id>urn:sha1:91196d76b7919fefa382b65f2416f4327435e3a1</id>
<content type='text'>
This is needed for a future patches to enable the new C23 language dialect.

Signed-off-by: Michael Neuling &lt;michaelneuling@tenstorrent.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Use fdt_driver for initialization</title>
<updated>2024-11-28T12:22:58Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-11T22:02:54Z</published>
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<id>urn:sha1:a524f0a507de18f150ea33ac923117291c6d1d81</id>
<content type='text'>
The serial driver subsystem does not need any extra data, so it can use
`struct fdt_driver` directly. The generic fdt_serial_init() first
attempts to match the chosen stdout device, and upon failure matches the
first available serial device in the DT. It is a fatal error if no such
device is found. This matches the behavior of fdt_driver_init_one().

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Pass the FDT to fdt_serial_init()</title>
<updated>2024-08-24T07:33:01Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-07-31T04:58:56Z</published>
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<id>urn:sha1:c36801841e366fa3ddeb7d7888b8691006c0b552</id>
<content type='text'>
Indicate that this function does not modify the FDT blob, and
deduplicate the call to fdt_get_address().

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Constify FDT pointers in parsing functions</title>
<updated>2024-08-24T07:32:46Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-07-31T04:58:51Z</published>
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<id>urn:sha1:bd76eb49502c25d3553da4aaeff846e8762a612d</id>
<content type='text'>
Indicate that none of these functions modify the devicetree by
constifying the parameter type.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Renesas SCIF driver</title>
<updated>2022-12-12T13:20:26Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:07Z</published>
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<id>urn:sha1:64e8b9f72e986aba25f7cb41218b1a1088042ae3</id>
<content type='text'>
Add Renesas SCIF driver.

Based on a patch in the BSP by Takeki Hamada
&lt;takeki.hamada.ak@bp.renesas.com&gt;
Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: add semihosting support</title>
<updated>2022-09-13T12:54:42Z</updated>
<author>
<name>Kautuk Consul</name>
<email>kconsul@ventanamicro.com</email>
</author>
<published>2022-09-12T10:52:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=7f09fba86e439808e0b40bdf536937c42e1ea2c9'/>
<id>urn:sha1:7f09fba86e439808e0b40bdf536937c42e1ea2c9</id>
<content type='text'>
We add RISC-V semihosting based serial console for JTAG based early
debugging.

The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Kautuk Consul &lt;kconsul@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Cadence UART driver</title>
<updated>2022-08-23T03:10:17Z</updated>
<author>
<name>Jun Liang Tan</name>
<email>junliang.tan@linux.starfivetech.com</email>
</author>
<published>2022-08-17T15:40:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=cbaa9b0333517b3c25bea8d1c71ac8005ff1f727'/>
<id>urn:sha1:cbaa9b0333517b3c25bea8d1c71ac8005ff1f727</id>
<content type='text'>
Add Cadence UART driver

Signed-off-by: Jun Liang Tan &lt;junliang.tan@linux.starfivetech.com&gt;
Signed-off-by: Wei Liang Lim &lt;weiliang.lim@linux.starfivetech.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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