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<title>opensbi.git/include/sbi_utils, branch master</title>
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<updated>2026-07-22T07:38:15Z</updated>
<entry>
<title>lib: utils/irqchip/imsic: embed sbi_irqchip_device in imsic data</title>
<updated>2026-07-22T07:38:15Z</updated>
<author>
<name>Pawandeep Oza</name>
<email>pawandeep.oza@oss.qualcomm.com</email>
</author>
<published>2026-07-21T21:48:27Z</published>
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<id>urn:sha1:22139b889dfeaa98d4b3f1abe4fd0b7c96f11b26</id>
<content type='text'>
Embed sbi_irqchip_device in struct imsic_data to enable instance-based
irqchip registration, replacing the previous global imsic_device
singleton. Include sbi_irqchip.h from imsic.h to make the embedded
struct visible to consumers.

Signed-off-by: Oza Pawandeep &lt;pawandeep.oza@oss.qualcomm.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260721214833.687361-4-pawandeep.oza@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent linking</title>
<updated>2026-07-22T07:38:13Z</updated>
<author>
<name>Pawandeep Oza</name>
<email>pawandeep.oza@oss.qualcomm.com</email>
</author>
<published>2026-07-21T21:48:26Z</published>
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<id>urn:sha1:759910326c3ac4cf9d42133fc1399d519037eae1</id>
<content type='text'>
Add parent_unique_id fields to struct aplic_data for
IMSIC parent linking in MSI mode. Store parent IMSIC unique_id
during FDT parsing of the APLIC node.

Add aplic_is_msi_mode() complementing aplic_is_direct_mode() to
consolidate delivery mode detection. Add APLIC_TARGET_EIID() macro
for packing the EIID field into the TARGET register.

Add parent_unique_id and parent_irq_map fields to struct aplic_data.
parent_unique_id identifies the upstream IMSIC irqchip device resolved
via sbi_irqchip_find_device() during hwirq_setup. parent_irq_map is
a per-source array allocated at cold init time to track the EIID
assigned by the IMSIC for each APLIC source.

Restore aplic_writel_msicfg() and re-introduce MSI address register
programming in aplic_init(), gated on aplic_is_msi_mode(). Set the
DOMAINCFG_DM bit to switch the hardware to MSI delivery mode when
no IDC structures are present.

Add aplic_program_msi_target() to pack hart_index, guest_index, and
EIID into the APLIC_TARGET register. Add aplic_write_msi() as the
sbi_irqchip write_msi callback that extracts EIID and hart_index from
the MSI message and calls aplic_program_msi_target(). Add
aplic_msi_callback() as the MSI receive callback that dispatches to
sbi_irqchip_process_hwirq() on the APLIC chip.

Extend aplic_hwirq_setup() with an MSI path that resolves the parent
IMSIC chip by parent_unique_id, registers an MSI route via
sbi_irqchip_register_msi(), and stores the allocated EIID in
parent_irq_map for the source being configured.

Extend aplic_hwirq_set_affinity() with an MSI path that delegates
affinity reprogramming to the parent IMSIC chip via
sbi_irqchip_set_affinity() using the stored parent_irq_map entry.

Guard warm_init, process_hwirqs, and hwirq_eoi with early returns in
MSI mode as interrupt delivery and acknowledgement are handled by the
IMSIC in that configuration.

Signed-off-by: Oza Pawandeep &lt;pawandeep.oza@oss.qualcomm.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260721214833.687361-3-pawandeep.oza@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/mpxy: Add RPMI MPXY driver for logging service group</title>
<updated>2026-07-01T16:00:24Z</updated>
<author>
<name>Subrahmanya Lingappa</name>
<email>subrahmanya.lingappa@oss.qualcomm.com</email>
</author>
<published>2026-06-19T10:34:24Z</published>
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<id>urn:sha1:262571217c75c649115633d8075cb6a40d940733</id>
<content type='text'>
Add RPMI MPXY proxy driver for LOGGING service group so that
S-mode can leverage LOGGING service group implemented by the
platform microcontroller.

Reviewed-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Signed-off-by: Subrahmanya Lingappa &lt;subrahmanya.lingappa@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260619103424.990954-1-subrahmanya.lingappa@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: utils/hsm: Add __noreturn attribute for sifive_cease</title>
<updated>2026-06-15T05:08:09Z</updated>
<author>
<name>Bo Gan</name>
<email>ganboing@gmail.com</email>
</author>
<published>2026-06-05T07:57:07Z</published>
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<id>urn:sha1:0f42eff6eaca80bd483292c8911292cbaa2341fd</id>
<content type='text'>
Decorate the sifive_cease to allow more compiler optimizations

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260605075708.96-2-ganboing@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Optimize extensions_init() to parse ISA extensions once</title>
<updated>2026-06-12T10:38:29Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-05-21T08:26:25Z</published>
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<id>urn:sha1:ecc92e87a990e3f45081fbf2c84ad342d9226aaa</id>
<content type='text'>
Instead of parsing ISA extensions separately for each hart in the
generic_extensions_init() function, it is better to parse ISA extensions
for all available harts in the cold boot path. Also, this allows us
to remove fdt_isa_bitmap from scratch space and directly initialize
"extensions" in struct sbi_hart_features for each hart.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260521082625.1520870-3-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: mailbox: Update RPMI notification structs and add performance events</title>
<updated>2026-06-10T12:43:10Z</updated>
<author>
<name>David E. Garcia Porras</name>
<email>david.garcia@aheadcomputing.com</email>
</author>
<published>2026-06-08T12:52:55Z</published>
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<id>urn:sha1:59fe435b2840da294fa054012ac23e26a8f325c0</id>
<content type='text'>
Add rpmi_event_notification_state enum with disable, enable, and return
current state IDs. Also, add req_state field to rpmi_enable_notification_req
and current_state field to rpmi_enable_notification_resp for RPMI specification
compliance.

Add notification event ID enum and data structures for RPMI Performance
service group events: power change, limit change, and level change.

Signed-off-by: David E. Garcia Porras &lt;david.garcia@aheadcomputing.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260608125257.3220114-4-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: mailbox: rpmi_msgprot: Add RPMI performance domain flag defines</title>
<updated>2026-06-07T11:16:56Z</updated>
<author>
<name>David E. Garcia Porras</name>
<email>david.garcia@aheadcomputing.com</email>
</author>
<published>2026-03-28T05:43:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=243035c565ac22a3d694247bd7fc324743999978'/>
<id>urn:sha1:243035c565ac22a3d694247bd7fc324743999978</id>
<content type='text'>
Add bit-field defines for the RPMI performance domain attributes flags
and fast-channel attributes flags as specified in the RPMI specification.
These are needed by platform implementations that provide RPMI
performance services (e.g. DVFS controllers).

Also add the missing db_write_value field to
rpmi_perf_get_fast_chn_attr_resp to match the RPMI spec layout.

Signed-off-by: David E. Garcia Porras &lt;david.garcia@aheadcomputing.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260328054347.3706029-5-david.garcia@aheadcomputing.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add MPXY client driver for RPMI MM service group</title>
<updated>2026-04-06T12:53:25Z</updated>
<author>
<name>Ranbir Singh</name>
<email>ranbir.singh@oss.qualcomm.com</email>
</author>
<published>2026-02-25T06:13:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=0b041e58c0787f76325da5081e41a13bf304d328'/>
<id>urn:sha1:0b041e58c0787f76325da5081e41a13bf304d328</id>
<content type='text'>
Add necessary infra for implementing RPMI Management Mode
service group on platform microcontroller.

Co-authored-by: Sunil V L &lt;sunilvl@oss.qualcomm.com&gt;
Signed-off-by: Ranbir Singh &lt;ranbir.singh@oss.qualcomm.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Add unique_id to plic, aplic, and imsic data</title>
<updated>2026-03-22T05:25:03Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-02-13T05:53:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=e82d20122dcf97a357053636c1fc6d268bd4db5c'/>
<id>urn:sha1:e82d20122dcf97a357053636c1fc6d268bd4db5c</id>
<content type='text'>
Add a 32-bit unique ID to plic, aplic, and imsic data which can be
used to differentiate multiple irqchip devices.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260213055342.3124872-7-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Add IDC to hartindex map in struct aplic_data</title>
<updated>2026-03-22T05:22:45Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-02-13T05:53:38Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=5a300b32d546d226e55361e47d07b1c9171f07c8'/>
<id>urn:sha1:5a300b32d546d226e55361e47d07b1c9171f07c8</id>
<content type='text'>
A platform can have multiple APLICs in direct-mode targetting
different subset of harts. Add APLIC ID to hartindex map in
struct aplic_data to capture the set of harts targeted by a
given APLIC in direct-mode.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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