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<title>opensbi.git/include/sbi_utils, branch v1.2</title>
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<id>http://cgit.235523.xyz/opensbi.git/atom/include/sbi_utils?h=v1.2</id>
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<updated>2022-12-17T03:33:30Z</updated>
<entry>
<title>lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers</title>
<updated>2022-12-17T03:33:30Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2022-12-11T06:54:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=9a2eeb4aaeac9102a7db3676035d83394784c88b'/>
<id>urn:sha1:9a2eeb4aaeac9102a7db3676035d83394784c88b</id>
<content type='text'>
Currently the context save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers</title>
<updated>2022-12-17T03:30:29Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2022-12-11T06:54:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=8509e46ca63a4ed7dff2244cd7f288bf5591ab61'/>
<id>urn:sha1:8509e46ca63a4ed7dff2244cd7f288bf5591ab61</id>
<content type='text'>
Currently the priority save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add FDT driver for Renesas SCIF</title>
<updated>2022-12-12T13:20:35Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:08Z</published>
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<id>urn:sha1:0021b437377b4ea95f567f91fbf506c0b0b9e227</id>
<content type='text'>
Add FDT driver for Renesas SCIF.

    dts example:

    soc: soc {
          ....
            scif0: serial@1004b800 {
                    compatible = "renesas,scif-r9a07g043",
                                 "renesas,scif-r9a07g044";
                    reg = &lt;0 0x1004b800 0 0x400&gt;;
                    interrupts = &lt;412 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;414 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;415 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;413 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;416 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;416 IRQ_TYPE_LEVEL_HIGH&gt;;
                    interrupt-names = "eri", "rxi", "txi",
                                      "bri", "dri", "tei";
                    clocks = &lt;&amp;cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK&gt;;
                    clock-names = "fck";
                    power-domains = &lt;&amp;cpg&gt;;
                    resets = &lt;&amp;cpg R9A07G043_SCIF0_RST_SYSTEM_N&gt;;
                    status = "disabled";
            };
          ....
    };

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Renesas SCIF driver</title>
<updated>2022-12-12T13:20:26Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:07Z</published>
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<id>urn:sha1:64e8b9f72e986aba25f7cb41218b1a1088042ae3</id>
<content type='text'>
Add Renesas SCIF driver.

Based on a patch in the BSP by Takeki Hamada
&lt;takeki.hamada.ak@bp.renesas.com&gt;
Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Add Andes fdt ipi driver support</title>
<updated>2022-10-23T05:01:01Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:50Z</published>
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<id>urn:sha1:ce7c490719ed4e268979c8b6b54a5252396fbb3b</id>
<content type='text'>
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.

Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.

dts example (Quad-core AX45MP):

  plicsw: interrupt-controller@e6400000 {
          compatible = "andestech,plicsw";
          reg = &lt;0x00000000 0xe6400000 0x00000000 0x00400000&gt;;
          interrupts-extended = &lt;&amp;CPU0_intc 3
                                 &amp;CPU1_intc 3
                                 &amp;CPU2_intc 3
                                 &amp;CPU3_intc 3&gt;;
          interrupt-controller;
          #address-cells = &lt;2&gt;;
          #interrupt-cells = &lt;2&gt;;
  };

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Add Andes fdt timer support</title>
<updated>2022-10-23T04:56:39Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=ef9f02e7fba47412d6c057ba78fd3d89cb4e5fc3'/>
<id>urn:sha1:ef9f02e7fba47412d6c057ba78fd3d89cb4e5fc3</id>
<content type='text'>
Since we can get the PLMT base address and timer frequency from
device tree, move plmt timer device to fdt timer framework.

dts example (Quad-core AX45MP):

  cpus {
      ...
      timebase-frequency = &lt;0x3938700&gt;;
      ...
  }
  soc {
      ...
      plmt0@e6000000 {
          compatible = "andestech,plmt0";
          reg = &lt;0x00 0xe6000000 0x00 0x100000&gt;;
          interrupts-extended = &lt;&amp;cpu0_intc 0x07
                                 &amp;cpu1_intc 0x07
                                 &amp;cpu2_intc 0x07
                                 &amp;cpu3_intc 0x07&gt;;
      };
      ...
  }

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add sbi_domain_root_add_memrange() API</title>
<updated>2022-10-23T04:51:21Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:42Z</published>
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<id>urn:sha1:dcdaf3027489cadd513767eda6dcaa0c1ecd2d29</id>
<content type='text'>
This patch generalizes the logic to add a memory range with desired
alignment and flags of consecutive regions to the root domain.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: add semihosting support</title>
<updated>2022-09-13T12:54:42Z</updated>
<author>
<name>Kautuk Consul</name>
<email>kconsul@ventanamicro.com</email>
</author>
<published>2022-09-12T10:52:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=7f09fba86e439808e0b40bdf536937c42e1ea2c9'/>
<id>urn:sha1:7f09fba86e439808e0b40bdf536937c42e1ea2c9</id>
<content type='text'>
We add RISC-V semihosting based serial console for JTAG based early
debugging.

The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Kautuk Consul &lt;kconsul@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Cadence UART driver</title>
<updated>2022-08-23T03:10:17Z</updated>
<author>
<name>Jun Liang Tan</name>
<email>junliang.tan@linux.starfivetech.com</email>
</author>
<published>2022-08-17T15:40:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=cbaa9b0333517b3c25bea8d1c71ac8005ff1f727'/>
<id>urn:sha1:cbaa9b0333517b3c25bea8d1c71ac8005ff1f727</id>
<content type='text'>
Add Cadence UART driver

Signed-off-by: Jun Liang Tan &lt;junliang.tan@linux.starfivetech.com&gt;
Signed-off-by: Wei Liang Lim &lt;weiliang.lim@linux.starfivetech.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: Use kconfig for enabling/disabling</title>
<updated>2022-08-08T04:04:08Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:04:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=68d7b85ec75119787d7c672062de5d29156c44be'/>
<id>urn:sha1:68d7b85ec75119787d7c672062de5d29156c44be</id>
<content type='text'>
We update FDT support makefile to use kconfig for enabling/disabling.
To avoid compilation errors, we also enable FDT for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
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