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<title>opensbi.git/include/sbi_utils, branch v1.5</title>
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<updated>2023-12-27T06:27:33Z</updated>
<entry>
<title>lib: utils/timer: mtimer: only use regname for aclint</title>
<updated>2023-12-27T06:27:33Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-12-27T00:46:11Z</published>
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<id>urn:sha1:ba29293dc947e13fa2e63de7ed289d7bb9b540f4</id>
<content type='text'>
The parser will fail if the timer is clint timer and has regname
property. As the regname is only meaningful for aclint, it is more
robust to only check regname for aclint timer.

Fixes: 6112d58 ("lib: utils/fdt: Allow to use reg-names when parsing ACLINT")
Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Add shared MMIO region for PLIC in root domain</title>
<updated>2023-12-19T10:26:37Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-12-11T08:37:56Z</published>
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<id>urn:sha1:cdebae2cc9539e2e0553b9c68eab22997c734cbb</id>
<content type='text'>
On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.

If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: Allow to use reg-names when parsing ACLINT</title>
<updated>2023-12-11T05:05:32Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-11-17T12:13:09Z</published>
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<id>urn:sha1:6112d584d435d2d2f2685cfcd8321c389056636b</id>
<content type='text'>
Currently, the fdt_parse_aclint_node() follows a fixed order to parse
ACLINT timer. This may cause the undesirable result when the ACLINT
device does not support mtime without adding an empty entry for it in
the DT.

To be robust, make fdt_parse_aclint_node() support "reg-names" property,
so it can parse the DT in an order independent way. For compatibility,
fdt_parse_aclint_node() only use "reg-names" when parsing ACLINT timer,
and will fallback to the old way if "reg-names" property is not found.

Link: https://lore.kernel.org/all/20231114-skedaddle-precinct-66c8897227bb@squawk/
Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable</title>
<updated>2023-12-06T12:45:41Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-11-30T12:42:10Z</published>
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<id>urn:sha1:0308f93dc44a21f11d5b54d449170b4142d9e473</id>
<content type='text'>
To allow platform override pmu_init() filling the translation table
fdt_pmu_evt_select[] when PMU node doesn't provide such information,
we need to share the table and its entry counter with other .c file.

We also define the structures of PMU property in fdt_helper.h, so we
can initialize the mappings in arrays.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme</title>
<updated>2023-12-06T11:53:27Z</updated>
<author>
<name>Leo Yu-Chi Liang</name>
<email>ycliang@andestech.com</email>
</author>
<published>2023-11-30T12:41:59Z</published>
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<id>urn:sha1:bd74931d79e1b81494a22b1ce368c935abbc0d2c</id>
<content type='text'>
The old scheme doesn't allow sending hart0 self-IPI as the
corresponding bit on pending register is hardwired to 0, this
could lead to unhandle IPIs on SMP systems, esp. on single-core.

Furthermore, the limitation of old scheme is 8-core, instead of
reserving source hart information, we assign bit (x + 1) as the
enable and pending bit of hartx, this also expands the bootable
hart number.

The following diagram shows the enable bits of the new scheme
on 32-core Andes platform.

   Pending regs: 0x1000  x---0---0---0---0------0---0
Pending hart ID:             0   1   2   3 ... 30  31
   Interrupt ID:         0   1   2   3   4 ... 31  32
                         |   |   |   |   |      |   |
    Enable regs: 0x2000  x---1---0---0---0-...--0---0---&gt; hart0
                         |   |   |   |   |      |   |
                 0x2080  x---0---1---0---0-...--0---0---&gt; hart1
                         |   |   |   |   |      |   |
                 0x2100  x---0---0---1---0-...--0---0---&gt; hart2
                         |   |   |   |   |      |   |
                 0x2180  x---0---0---0---1-...--0---0---&gt; hart3
                         .   .   .   .   .      .   .
                         .   .   .   .   .      .   .
                         .   .   .   .   .      .   .
                 0x2f00  x---0---0---0---0-...--1---0---&gt; hart30
                         |   |   |   |   |      |   |
                 0x2f80  x---0---0---0---0-...--0---1---&gt; hart31
                         &lt;-------- word 0 -------&gt;&lt;--- word 1 ---&gt;

To send IPI to hart0, for example, another hart (including hart0
itself) will set bit 1 of first word on the pending register.

We also fix indentation in andes_plicsw.h along with this patch.

Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support")
Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Randolph &lt;randolph@andestech.com&gt;
Reported-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html
Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Tested-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/reset: Remove SiFive Test reset driver</title>
<updated>2023-07-31T08:39:24Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-07-21T12:50:27Z</published>
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<id>urn:sha1:c2e602707dc0f915e96b8726d63d569cbb6724b4</id>
<content type='text'>
The functionality of SiFive Test reset driver is easily available
through Syscon reset driver so let us remove the SiFive Test driver.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/regmap: Add simple FDT based regmap framework</title>
<updated>2023-07-31T08:39:10Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-07-21T08:09:57Z</published>
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<id>urn:sha1:8e97275d97bbfb9b990a5e7beafe99bea0e3f538</id>
<content type='text'>
We add a simple FDT based regmap framework which is built on top of
generic regmap library. The phandle of FDT regmap DT node is treated
as unique regmap ID. The FDT based regmap drivers will be probed
on-demand from fdt_regmap_get_by_phandle() and fdt_regmap_get()
called by the regmap client drivers.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/regmap: Add generic regmap access library</title>
<updated>2023-07-31T08:39:08Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-07-21T08:09:50Z</published>
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<id>urn:sha1:14a35b0e0e8ceaeb664c5078d6a1fec9e7193c72</id>
<content type='text'>
We add generic regmap access library which is independent of
hardware description format (FDT or ACPI). The OpenSBI platform
support or regmap drivers can register regmap instances which
can be discovered by different regmap clients based on the
unique ID of regmap instances.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>include: sbi_utils: Remove driver pointer from struct i2c_adapter</title>
<updated>2023-07-31T08:39:06Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-07-21T08:09:43Z</published>
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<id>urn:sha1:44c5151293849736118090bf5230d6b298a9d0b0</id>
<content type='text'>
The "driver" pointer in struct i2c_adapter is not used anywhere
so let us remove it.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add detection of Smepmp from ISA string in FDT</title>
<updated>2023-07-13T06:42:58Z</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2023-07-12T04:34:31Z</published>
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<id>urn:sha1:d72f5f17478dfef3df817339a0f02cfdb77a1dc1</id>
<content type='text'>
- Add function to parse ISA string in FDT.
- Set Smepmp feature bit in extensions if "smepmp" string is found in ISA string.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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