opensbi.git/include/sbi_utils, branch v1.8

include: Fix LLVM compile error in sbi_utils/hsm/fdt_hsm_sifive_inst.h

2025-12-28T15:17:12Z

Currently, OpenSBI fails to compile for LLVM=1 using 2025.11.27 riscv-gnu-toolchain with the following error: In file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20: opensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:17:23: error: expected instruction format 17 | __asm__ __volatile__(".insn 0xfc000073" ::: "memory"); | ^ :1:8: note: instantiated into assembly here 1 | .insn 0xfc000073 | ^ In file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20: opensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:12:23: error: expected instruction format 12 | __asm__ __volatile__(".insn 0x30500073" ::: "memory"); | ^ :1:8: note: instantiated into assembly here 1 | .insn 0x30500073 | ^ 2 errors generated. To fix this compile error, use ".word" in-place ".insn". Fixes: 1514a327306b ("lib: utils/hsm: Add SiFive TMC0 driver") Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20251227100916.327524-1-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/serial: Support multiple UART8250 devices

2025-12-21T15:32:44Z

Previously we assume only 1 UART8250 instance can be used. Now we support multiple instances by introducing counterpart functions to putc/getc/init which take an extra *dev parameter, and name them as uart8250_device_xyz() The original functions without the *dev parameter will operate on the default instance exactly the same as before, so no changes on the caller is required. Note: uart8250_device_init only does device initialization without the console registration logic. Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251218104243.562667-7-ganboing@gmail.com Signed-off-by: Anup Patel

lib: utils: Add MPXY RPMI mailbox driver for performance

2025-11-04T05:05:59Z

Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel

lib: utils: Add MPXY RPMI mailbox driver for device power

2025-11-04T05:04:01Z

Add MPXY RPMI mailbox driver for device power. Signed-off-by: Joshua Yeong Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20251013153138.1574512-3-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel

lib: utils: Add MPXY RPMI mailbox driver for voltage

2025-11-04T05:02:57Z

Add voltage service group for RPMI/MPXY support Signed-off-by: Joshua Yeong Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20251013153138.1574512-2-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel

lib: utils/suspend: Add SiFive SMC0 driver

2025-10-28T05:58:10Z

The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang Reviewed-by: Anup Patel Signed-off-by: Nick Hu Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils/timer: Expose timer update function

2025-10-28T05:58:06Z

Exposing the ACLINT timer update APIs so the user can update the mtimer after waking up from the non-retentive suspend. Reviewed-by: Cyan Yang Reviewed-by: Anup Patel Signed-off-by: Nick Hu Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-10-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils/hsm: Add SiFive TMC0 driver

2025-10-28T05:58:03Z

The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Reviewed-by: Cyan Yang Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils/irqchip: Add APLIC restore function

2025-10-28T05:57:59Z

Since the APLIC may enter a reset state upon system wake-up from a platform low power state, adding a restore function to reinitialize the APLIC. Reviewed-by: Yong-Xuan Wang Reviewed-by: Cyan Yang Reviewed-by: Anup Patel Signed-off-by: Nick Hu Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-7-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Add fdt cmo helpers

2025-10-28T05:57:53Z

Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu Reviewed-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com Signed-off-by: Anup Patel