opensbi.git/include/sbi_utils, branch v1.9

include: utils/hsm: Add __noreturn attribute for sifive_cease

2026-06-15T05:08:09Z

Decorate the sifive_cease to allow more compiler optimizations Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260605075708.96-2-ganboing@gmail.com Signed-off-by: Anup Patel

platform: generic: Optimize extensions_init() to parse ISA extensions once

2026-06-12T10:38:29Z

Instead of parsing ISA extensions separately for each hart in the generic_extensions_init() function, it is better to parse ISA extensions for all available harts in the cold boot path. Also, this allows us to remove fdt_isa_bitmap from scratch space and directly initialize "extensions" in struct sbi_hart_features for each hart. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260521082625.1520870-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

include: mailbox: Update RPMI notification structs and add performance events

2026-06-10T12:43:10Z

Add rpmi_event_notification_state enum with disable, enable, and return current state IDs. Also, add req_state field to rpmi_enable_notification_req and current_state field to rpmi_enable_notification_resp for RPMI specification compliance. Add notification event ID enum and data structures for RPMI Performance service group events: power change, limit change, and level change. Signed-off-by: David E. Garcia Porras Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260608125257.3220114-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

include: mailbox: rpmi_msgprot: Add RPMI performance domain flag defines

2026-06-07T11:16:56Z

Add bit-field defines for the RPMI performance domain attributes flags and fast-channel attributes flags as specified in the RPMI specification. These are needed by platform implementations that provide RPMI performance services (e.g. DVFS controllers). Also add the missing db_write_value field to rpmi_perf_get_fast_chn_attr_resp to match the RPMI spec layout. Signed-off-by: David E. Garcia Porras Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260328054347.3706029-5-david.garcia@aheadcomputing.com Signed-off-by: Anup Patel

lib: utils: Add MPXY client driver for RPMI MM service group

2026-04-06T12:53:25Z

Add necessary infra for implementing RPMI Management Mode service group on platform microcontroller. Co-authored-by: Sunil V L Signed-off-by: Ranbir Singh Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip: Add unique_id to plic, aplic, and imsic data

2026-03-22T05:25:03Z

Add a 32-bit unique ID to plic, aplic, and imsic data which can be used to differentiate multiple irqchip devices. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-7-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip: Add IDC to hartindex map in struct aplic_data

2026-03-22T05:22:45Z

A platform can have multiple APLICs in direct-mode targetting different subset of harts. Add APLIC ID to hartindex map in struct aplic_data to capture the set of harts targeted by a given APLIC in direct-mode. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/serial: Add support for Altera JTAG UART

2026-02-20T11:20:35Z

Altera provides a JTAG UART core that provides virtual UART over JTAG and can coexist with their virtual JTAG. [1] This core has already been supported by Linux and the programming interface has always been stable. Add support for it to OpenSBI to ease JTAG prototype bringing up. The driver follows the device tree binding in mainline Linux. [2] [1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core [2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn Signed-off-by: Anup Patel

lib: utils/suspend: add Andes ATCSMU suspend driver

2026-02-11T06:44:04Z

Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie Signed-off-by: Leo Yu-Chi Liang Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel

lib: utils/cache: add Andes last level cache controller

2026-02-11T06:43:01Z

Introduce a FDT-based driver for the Andes Last Level Cache (LLC) controller to support cache maintenance operations. Signed-off-by: Ben Zong-You Xie Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com Signed-off-by: Anup Patel