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<title>opensbi.git/include, branch v1.5</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/include?h=v1.5</id>
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<updated>2024-06-30T08:33:26Z</updated>
<entry>
<title>include: Bump-up version to 1.5</title>
<updated>2024-06-30T08:33:26Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-06-30T08:33:26Z</published>
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<id>urn:sha1:455de672dd7c2aa1992df54dfb08dc11abbc1b1a</id>
<content type='text'>
This patch updates OpenSBI version to 1.5 as part of
release preparation.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: add support for firmware features extension</title>
<updated>2024-06-19T12:39:22Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-06-19T09:42:39Z</published>
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<id>urn:sha1:aa5a8593696b39059832d12455c31dcfeb4d9259</id>
<content type='text'>
This extension allows the software running in supervisor mode to control
the behavior of various features of the SBI [1]. Implement the support
for such extension.

Link: https://lists.riscv.org/g/tech-prs/message/924 [1]
Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add support for Svade and Svadu extensions</title>
<updated>2024-06-18T11:11:32Z</updated>
<author>
<name>Yong-Xuan Wang</name>
<email>yongxuan.wang@sifive.com</email>
</author>
<published>2024-06-05T12:11:09Z</published>
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<id>urn:sha1:53844c98d082cbba29a6e568196add6de95e858f</id>
<content type='text'>
Add support for Svade and Svadu extensions. When both are present in the
device tree, the M-mode firmware should select the Svade extension
to comply with the RVA23 profile, which mandates Svade and lists Svadu as
an optional extension.

Signed-off-by: Yong-Xuan Wang &lt;yongxuan.wang@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>sbi: sbi_domain_context: Fix trap context for domain context switching</title>
<updated>2024-06-13T13:51:27Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2024-06-07T11:39:28Z</published>
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<id>urn:sha1:3a94a3258039f225d068cb575844062c3f86bc03</id>
<content type='text'>
Save/restore sbi_trap_context during domain context switching to
ensure proper trap handling and isolation. This maintains correct
domain-specific state, avoiding context corruption.

Fixes: abea949721bc ("lib: sbi: Introduce trap context")
Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Alvin Chang &lt;alvinga@andestech.com&gt;
Tested-by: Alvin Chang &lt;alvinga@andestech.com&gt;
Reviewed-by: Yong Li &lt;yong.li@intel.com&gt;
Tested-by: Yong Li &lt;yong.li@intel.com&gt;
</content>
</entry>
<entry>
<title>sbi: sbi_domain_context: Add spinlock for updating domain assigned_harts</title>
<updated>2024-05-07T14:41:30Z</updated>
<author>
<name>Alvin Chang</name>
<email>alvinga@andestech.com</email>
</author>
<published>2024-04-16T05:02:13Z</published>
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<id>urn:sha1:17e829129d60d7d178d47ecbd8990e705690d352</id>
<content type='text'>
Add spinlock protection to avoid race condition on assigned_harts
during domain context switching. Also, rename/add variables for
accessing the corresponding domain of target/current context.

Signed-off-by: Alvin Chang &lt;alvinga@andestech.com&gt;
Reviewed-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: sse: fix typos, comments and spacing errors</title>
<updated>2024-05-07T11:54:11Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-04-09T10:02:02Z</published>
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<id>urn:sha1:c21c99db6acf14fdf420271ce670b6a648fc3a9a</id>
<content type='text'>
Fix some errors spotted by Samuel while reviewing the SSE implementation.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reported-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: tests: Add test suite init function</title>
<updated>2024-05-07T05:57:13Z</updated>
<author>
<name>Ivan Orlov</name>
<email>ivan.orlov0322@gmail.com</email>
</author>
<published>2024-04-23T15:52:43Z</published>
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<id>urn:sha1:f6243d9ce591b3a2085feff23ab2fbe1a6d51a14</id>
<content type='text'>
Allow to define an init function for the test suite. It could help us
to initialize global variable once, and use them in multiple test cases
after the initialization.

For instance, if multiple test cases use the same atomic_t var, it
could be helpful to call ATOMIC_INIT once during the suite
initialization.

Signed-off-by: Ivan Orlov &lt;ivan.orlov0322@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Simplify wait_for_coldboot() implementation</title>
<updated>2024-04-05T12:18:23Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-03-15T14:25:23Z</published>
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<id>urn:sha1:beb0cd177f10a6bdafd73aac19059fecf6a07a91</id>
<content type='text'>
On QEMU virt machine with large number of HARTs, some of the HARTs
randomly fail to come out of wait_for_coldboot() due to one of the
following race-conditions:

1) Failing HARTs are not able to acquire the coldboot_lock and
   update the coldboot_hartmask in wait_for_coldboot() before
   the coldboot HART acquires the coldboot_lock and sends IPI
   in wake_coldboot_harts() hence the failing HARTs never
   receive IPI from the coldboot HART.

2) Failing HARTs acquire the coldbood_lock and update the
   coldboot_hartmask before coldboot HART does sbi_scratch_init()
   so the sbi_hartmask_set_hartid() does not update the
   coldboot_hartmask on the failing HARTs hence they never
   receive IPI from the coldboot HART.

To address this, use a simple busy-loop in wait_for_coldboot() for
polling on coldboot_done flag.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>include: sbi: Support byteorder macros in assembly</title>
<updated>2024-04-05T11:53:51Z</updated>
<author>
<name>Vivian Wang</name>
<email>dramforever@live.com</email>
</author>
<published>2024-03-15T17:36:39Z</published>
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<id>urn:sha1:5c9a73565f5e6d07cf30ecd7fa511d872050bd2c</id>
<content type='text'>
Avoid using C types and casts if sbi/sbi_byteorder.h is included in
assembly code

Signed-off-by: Vivian Wang &lt;dramforever@live.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add SSE support for PMU events</title>
<updated>2024-04-05T11:39:39Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-03-21T15:57:18Z</published>
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<id>urn:sha1:06fc453ec13de75e156261e8fe4073334d0e00c2</id>
<content type='text'>
Add SSE callbacks registration to PMU driver in order to disable
interrupt delegation for PMU interrupts. When interrupts are
undelegated send the PMU SSE event upon LCOFIP IRQ.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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