opensbi.git/lib/sbi/objects.mk, branch master

lib: sbi: add UBSan support

2026-06-12T06:28:35Z

UBSan (Undefined Behavior Sanitizer) is a tool implemented using compiler instrumentation at runtime that allows checking for statements whose output is not deterministic or defined by the C standard. Compiling and running OpenSBI with UBSan instrumentation will print a message in the console if any sentence performs such an action. Support involves two main components: 1. The UBSan implementation hooks (derived from NetBSD), used by the compiler to handle the check output. 2. A test suite integrated with the SBI unit test framework to verify correct operation at runtime. Usage: make UBSAN=y PLATFORM=generic ... The test suite is built when both UBSAN=y and CONFIG_SBIUNIT=y are enabled. When UBSan is enabled, FW_PAYLOAD_OFFSET may need to be increased due to the size increase added by the instrumentation. A value of 0x400000 has been tested. UBSan adds runtime overhead and is intended for development builds only, not for production. Note: This patch marks __stack_chk_guard in sbi_init.c as a weak symbol to prevent multiple definition errors at compile time with UBSan instrumentation enabled. This resolves the conflict between the .globl definitions in sbi_init.c and test_head.S. Signed-off-by: Marcos Oduardo Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260515163321.2038366-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel

lib: sbi: Move RISC-V PMP encoding functions to sbi_pmp.c

2026-06-10T07:47:30Z

Create a new file for handling the RISC-V PMP format and the new pmp_t type, as opposed to hart PMP CSR specific access. Signed-off-by: Nicholas Piggin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260430045528.420437-4-npiggin@gmail.com Signed-off-by: Anup Patel

lib: sbi: Add floating-point context save/restore support.

2026-05-18T08:32:28Z

Add support for saving and restoring RISC-V floating-point (F/D) extension state in OpenSBI. This introduces a floating-point context structure and helper routines to perform full context save and restore. The floating-point context includes storage for all 32 FPi registers (f0–f31) along with the fcsr control and status register. The register state is saved and restored using double-precision load/store instructions (fsd/fld), and single-precision load/store instructions (fsw/flw) on an RV64 system with F and D-extension support. The implementation follows an eager context switching model where the entire FP state is saved and restored on every context switch. This avoids the need for trap-based lazy management and keeps the design simple and deterministic. Signed-off-by: Dave Patel Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260518083023.997323-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi: Add RISC-V vector context save/restore support

2026-05-18T08:32:28Z

Eager context switch: Add support for saving and restoring RISC-V vector extension state in OpenSBI. This introduces a per-hart vector context structure and helper routines to perform full context save and restore. The vector context includes vcsr CSRs along with storage for all 32 vector registers. The register state is saved and restored using byte-wise vector load/store instructions (vs8r/vl8r). The implementation follows an eager context switching model where the entire vector state is saved and restored on every context switch. This provides a simple and deterministic mechanism without requiring lazy trap-based management. Signed-off-by: Dave Patel Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260518083023.997323-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi: Factor-out PMP programming into separate sources

2025-12-16T14:46:47Z

The PMP programming is a significant part of sbi_hart.c so factor-out this into separate sources sbi_hart_pmp.c and sbi_hart_pmp.h for better maintainability. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20251209135235.423391-6-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: sbi: Introduce hart protection abstraction

2025-12-16T14:46:47Z

Currently, PMP and ePMP are the only hart protection mechanisms available in OpenSBI but new protection mechanisms (such as Smmpt) will be added in the near future. To allow multiple hart protection mechanisms, introduce hart protection abstraction and related APIs. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20251209135235.423391-3-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: Emulate AMO instructions when Zaamo is not available

2025-05-20T03:48:03Z

The AMO instructions are very critical for Linux so allow low-end RISC-V implementations without Zaamo to boot Linux by emulating AMO instructions using Zalrsc when OpenSBI is compiled without Zaamo. Signed-off-by: Chao-ying Fu Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20250519121207.976949-1-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: sbi_misaligned_ldst: Add handling of vector load/store

2024-12-06T12:13:06Z

Add misaligned load/store handling for the vector extension to the sbi_misaligned_ldst library. This implementation is inspired from the misaligned_vec_ldst implementation in the riscv-pk project. Co-developed-by: Zong Li Signed-off-by: Zong Li Signed-off-by: Nylon Chen Reviewed-by: Andy Chiu Reviewed-by: Anup Patel

lib: sbi: Implement SBI MPXY extension

2024-12-06T03:56:52Z

Implement the SBI MPXY extension which provides an SBI interface to the supervisor software for send messages via MPXY framework. Signed-off-by: Rahul Pathak Co-developed-by: Anup Patel Signed-off-by: Anup Patel

lib: sbi: Add SBI Message Proxy (MPXY) framework

2024-12-06T03:56:50Z

Introduce SBI Message Proxy (MPXY) framework which allows platform specific code or drivers to register message protocol specific channels. This framework enables the supervisor software to send messages belonging to different message protocols via OpenSBI firmware. Signed-off-by: Rahul Pathak Co-developed-by: Himanshu Chauhan Signed-off-by: Himanshu Chauhan Co-developed-by: Anup Patel Signed-off-by: Anup Patel