opensbi.git/lib/sbi/riscv_asm.c, branch v1.0

lib: sbi: simplify pmp_set(), pmp_get()

2021-12-22T03:35:05Z

pmpcfg_csr and pmpcfg_shift are only negative for an unexpected value of __riscv_xlen. We can immediately return in this case. Signed-off-by: Heinrich Schuchardt Reviewed-by: Dong Du Reviewed-by: Anup Patel

lib: sbi: Improve fatal error handling

2021-12-02T03:20:36Z

BUG and BUG_ON are not informative and are rather lazy interfaces, only telling the user that something went wrong in a given function, but not what, requiring the user to find the sources corresponding to their firmware (which may not be available) and figure out how that BUG(_ON) was hit. Even SBI_ASSERT in its current form, which does include the condition that triggered it in the output, isn't necessarily very informative. In some cases, the error may be fixable by the user, but they need to know the problem in order to have any hope of fixing it. It's also a nuisance for developers, whose development trees may have changed significantly since the release in question being used, and so line numbers can make it harder for them to understand which error case a user has hit. This patch introduces a new sbi_panic function which is printf-like, allowing detailed error messages to be printed to the console. BUG and BUG_ON are removed, since the former is just a worse form of sbi_panic and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is augmented to take a set of arguments to pass to sbi_panic on failure, used like so (sbi_boot_print_hart's current error case, which currently manually calls sbi_printf and sbi_hart_hang): SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen)); The existing users of BUG are replaced with calls to sbi_panic along with informative error messages. BUG_ON and SBI_ASSERT were unused (and, in the case of SBI_ASSERT, remain unused). Many existing users of sbi_hart_hang should be converted to use either sbi_panic or SBI_ASSERT after this commit. Signed-off-by: Jessica Clarke Reviewed-by: Anup Patel Reviewed-by: Xiang W Reviewed-by: Atish Patra

lib: sbi: clear pmpcfg.A before setting in pmp_set()

2021-11-12T06:49:00Z

We should clear A bits in prot variable before enabling A_NA4 or A_NAPOT. Signed-off-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Update csr_read/write_num for PMU

2021-11-11T12:09:38Z

The Sscofpmf extension introduces mhpmevent[h] csrs to handle filtering /overflow bits in RV32. There is no way to read/write mcountinhibit using mcountinhibit csr using a variable. Updated the support to read/write mhpmevent[h] and mcountinhibit csr. Reviewed-by: Anup Patel Reviewed-by: Bin Meng Signed-off-by: Atish Patra

lib: sbi: Add BUG() macro for csr_read/write_num() and misa_string()

2021-09-22T08:08:39Z

We use BUG() macro in csr_read_num(), csr_write_num(), and misa_string() functions for unhandled cases. Signed-off-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: fix ctz bug

2021-09-22T07:56:23Z

The original version of ctz will cause an endless loop, if the parameter passed in is 0. This commit fixes this bug. Signed-off-by: Xiang W Reviewed-by: Bin Meng Reviewed-by: Anup Patel

lib: sbi: Use csr_read/write_num to read/update PMU counters

2021-07-11T04:50:44Z

Currently, csr_read/write_num functions are used to read/write PMP related CSRs where CSR value is decided at runtime. Expand this function to include PMU related CSRs as well. Reviewed-by: Anup Patel Reviewed-by: Xiang W Signed-off-by: Atish Patra

lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API

2020-09-16T03:35:25Z

We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Improve PMP CSR detection and progamming

2020-09-01T04:58:28Z

As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Fix 32/64 bits variable compatibility

2020-06-20T03:17:11Z

On RV64,"unsigned long" is 64bit and "unsigned int" is 32bit. So in function "pmp_get" and "pmp_set", if "pmpcfg_shift >= 32", "0xff << pmpcfg_shift" will go beyond "unsigned int" width. This patch tries to fix this issue. In function 'pmp_get': cfgmask = (0xff << pmpcfg_shift); --> cfgmask = (0xffUL << pmpcfg_shift); In function 'pmp_set': cfgmask = ~(0xff << pmpcfg_shift); --> cfgmask = ~(0xffUL << pmpcfg_shift); Signed-off-by: Liush Reviewed-by: Anup Patel