opensbi.git/lib/sbi/riscv_atomic.c, branch master

lib: Use proper add opcode on RV32 with Zalrsc

2026-03-10T05:17:23Z

The addw opcode is only defined in RV64, which produces 32-bit results. On RV32, the default add opcode already produces 32-bit results. Fixes: 995f226f3f33 ("lib: Emit lr and sc instructions based on -march flags") Signed-off-by: Marti Alonso Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com Signed-off-by: Anup Patel

lib: atomics: fix AMO test macros

2025-12-28T15:14:03Z

The "RISC-V C API" [1] defines architecture extension test macros says naming rule for the test macros is __riscv_, where is all lower-case. Three extensions dealing with atomics implementation are: "zaamo" consists of AMO instructions, "zalrsc" - LR/SC, "a" extension means both "zaamo" and "zalrsc" Built-in test macros are __riscv_a, __riscv_zaamo and __riscv_zalrsc. Alternative to the __riscv_a macro name, __riscv_atomic, is deprecated. Use correct test macro __riscv_zaamo for the AMO variant of atomics. It used to be __riscv_atomic that is both deprecated and incorrect because it tests for the "a" extension; i.e. both "zaamo" and "zalrsc" If ISA enables only zaamo but not zalrsc, code as it was would not compile. Older toolchains may have neither __riscv_zaamo nor __riscv_zalrsc, so query __riscv_atomic - it should be treated as both __riscv_zaamo and __riscv_zalrsc, in all present cases __riscv_zaamo is more favorable so take is as alternative for __riscv_zaamo [1] https://github.com/riscv-non-isa/riscv-c-api-doc Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251228073321.1533844-1-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel

lib: Emit lr and sc instructions based on -march flags

2025-03-28T13:22:05Z

When -march=rv64im_zalrsc_zicsr is used, provide atomic operations and locks using lr and sc instructions only. Signed-off-by: Chao-ying Fu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250226014727.19710-1-cfu@mips.com Signed-off-by: Anup Patel

lib: sbi: Replace __atomic_op_bit_ord with __atomic intrinsics

2023-12-08T08:36:40Z

Simplify atomic-related bit operations through __atomic intrinsics. Signed-off-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Fix __atomic_op_bit_ord and comments

2023-12-08T08:17:31Z

The original code returns the value of the word before modification. When modifying the upper 32 bits under RV64, the value returned via int return will have no meaning. Corrected to return the value of the bit. And modify the function description. Signed-off-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Remove xchg/cmpxchg implemented via lr/sc

2023-12-08T05:24:35Z

lr/sc is part of the A extension. If the A extension is not supported, lr/sc cannot be used. So remove xchg/cmpxchg. Signed-off-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: fix atomic_add_return

2021-04-09T13:21:02Z

The unsigned length may be 4 bytes or 8 bytes, amoadd.w only applies to 4 bytes hence this patch. Signed-off-by: Xiang W Reviewed-by: Anup Patel

include: Use more consistent name for atomic xchg() and cmpxchg()

2020-03-28T08:02:38Z

We should remove the "arch_" prefix from atomic xchg() and cmpxchg() function names to have consistent naming of all atomic functions. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Fix coding style issues

2020-03-10T04:57:28Z

This fixes various coding style issues found in the SBI codes. No functional changes. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

include: Move bits related defines and macros to sbi_bitops.h

2020-03-08T05:36:18Z

The right location for all bits related defines and macros is sbi_bitops.h hence this patch. With this patch, the sbi_bits.h is redundant so we remove it. Signed-off-by: Anup Patel Reviewed-by: Atish Patra